CHAPTER 9 TIMER/COUNTER FUNCTION
241
User’s Manual U15195EJ5V0UD
Figure 9-19. Change Timing from 100% Duty State (PWM Mode 0) (1/2)
(a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2)
CM0n3
TM0n
count value
BFCM0nx
CM0nx
DTMnx
F/F
Interrupt request
Positive phase
(TO0n0, TO0n2, TO0n4)
Negative phase
(TO0n1, TO0n3, TO0n5)
0000H
0000H
b
c
a
a
0000H
0000H
Note
b
CM0n3
CM0n3
a
a
CM0nx
match
CM0nx
match
CM0nx
match
CM0n3
b
b
CM0nx
match
CM0nx
match
CM0nx
match
t
t
t
t
t
t
INTTM0n
INTCM0n3
INTCM01x INTCM01x
INTCM01x
INTCM01x
INTCM01x INTCM01x
INTCM0n3
INTCM0n3
INTCM0n3
INTTM0n
INTTM0n
INTTM0n
Note
F/F is reset upon INTTM0n occurrence.
Remarks 1.
n = 0, 1
2.
x = 0 to 2
3.
t: Dead time = (DTRRn + 1)/f
CLK
(f
CLK
: Base clock)
4.
The above figure shows an active-high case.
5.
INTCM01x is generated on a match between TM01 and CM01x (a and b in the above figure).
INTCM00x is not generated.
Содержание PD703114
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