APPENDIX D REVISION HISTORY
686
User's Manual U15195EJ5V0UD
D.2 Revision History up to Previous Edition
The following table shows the revision history up to the previous edition. The “Applied to:” column indicates the
chapters of each edition in which the revision was applied.
(1/7)
Edition
Major Revision up to Previous Edition
Applied to:
Change of description on memory space in
1.2 Features
Change of description on regulator in
1.2 Features
Deletion of
Note
in
1.4 Ordering Information
CHAPTER 1
INTRODUCTION
Change of ASTB (PCT6) pin status in
2.2 Pin Status
Change of I/O circuit type from 5-K to 5-AC in
2.4 Types of Pin I/O Circuits and Connection
of Unused Pins
Change of I/O circuit type from 5-K to 5-AC in
2.5 Pin I/O Circuits
CHAPTER 2 PIN
FUNCTIONS
Modification of
Figure 3-3 Memory Map
Addition and deletion of description in
3.4.5 (2) Internal RAM area
Modification of description in
3.4.5 (4) External memory area
Deletion of description in
3.4.7 (1) Program space
Deletion of part of description in example of wrap-around application in
3.4.7 (2) Data space
Modification of
Figure 3-5 Recommended Memory Map
Addition and modification of description in
3.4.8 Peripheral I/O registers
Addition and modification of description in
3.4.10 System wait control register (VSWC)
CHAPTER 3 CPU
FUNCTION
Addition and modification of description in
4.2.1 Pin status during internal ROM, internal
RAM, and peripheral I/O access
Addition and modification of description in
4.3 Memory Block Function
Addition of
4.3.1 Chip select control function
Addition of description in
4.4.1 (1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1)
Addition of indication of
Note
in
4.5.1 Number of access clocks
Addition of
4.5.2 Bus sizing function
Addition of description in
4.6.1 (1) Data wait control registers 0, 1 (DWC0, DWC1)
Addition of description in
4.6.1 (2) Address wait control register (AWC)
Change of timing in
Figure 4-2 Example of Wait Insertion
Addition of description in
4.7 (1) Bus cycle control register (BCC)
CHAPTER 4 BUS
CONTROL
FUNCTION
Addition of description in
6.3.3 DMA byte count registers 0 to 3 (DBC0 to DBC3)
Change of description when DS1, DS0 bits = 1, 0 in
6.3.4 DMA addressing control registers
0 to 3 (DADC0 to DADC3)
Addition of
Cautions
in
6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)
Change of description on bit that can be manipulated in
6.3.6 DMA disable status register
(DDIS)
Change of description on bit that can be manipulated in
6.3.7 DMA restart register (DRST)
Addition of description in
6.5.1 Single transfer mode
Addition of description in
6.5.2 Single-step transfer mode
Change of transfer status when transfer target is in internal RAM in
Table 6-1 Relationship
Between Transfer Type and Transfer Target
Addition of
Caution
in
6.8 DMA Channel Priorities
2nd
Addition of
6.14 (5) DMA start factors
CHAPTER 6 DMA
FUNCTIONS (DMA
CONTROLLER)
Содержание PD703114
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