Rev. 3.0, 03/01, page x of xiii
Table 18-28. HcInterruptDisable Register ...................................................................................322
Table 18-29. HcHCCA Register ..................................................................................................323
Table 18-30. HcPeriodCurrentED Register..................................................................................323
Table 18-31. HcControlHeadED..................................................................................................323
Table 18-32. HcControlCurrentED Register................................................................................324
Table 18-33. HcBulkHeadED Register ........................................................................................324
Table 18-34. HcBulkCurrentED Register ....................................................................................324
Table 18-35. HcDoneHead Register ............................................................................................325
Table 18-36. HcFmInterval Register............................................................................................325
Table 18-37. HcFrameRemaining Register..................................................................................326
Table 18-38. HcFmNumberb Register .........................................................................................326
Table 18-39. HcPeriodicStart Register.........................................................................................326
Table 18-40. HcLSThreshold Register.........................................................................................327
Table 18-41. HcRhDescriptorA Register .....................................................................................328
Table 18-42. HcRhDescriptorB Register .....................................................................................329
Table 18-43. HcRhStatus Register ...............................................................................................330
Table 18-44. HcRhPortStatus Register ........................................................................................331
Table 19-1. A/D Converter Pins...................................................................................................334
Table 19-2. A/D Converter Registers...........................................................................................335
Table 19-3. Analog Input Channels and A/D Data Registers.......................................................336
Table 19-4. A/D Conversion Time (Single Mode).......................................................................344
Table 19-5. A/D Conversion Characteristics ...............................................................................345
Table 19-6. Analog Input Pin Characteristics ..............................................................................346
Table 20-1. DC Electrical Characteristics (Ta=0
°
C to 70
°
C) ......................................................347
Table 20-2. CPU Interface AC Timing Spec. .............................................................................349
Table 20-3. Crystal/Oscillator and PLL Settle AC Timing Spec. ...............................................349
Table 20-4. GPIO AC Timing Spec. ...........................................................................................349
Table 20-5. I/O Port Interrupt AC Timing Spec. ........................................................................350
Table 20-6. PCMCIA AC Timing Spec. .....................................................................................350
Table 20-7. UART AC Timing Spec. .........................................................................................350
Table 20-8. Parallel Port AC Timing Spec. ................................................................................351
Table 20-9. SCDI AC Timing Spec. ...........................................................................................351
Table 20-10. AFE Interface AC Timing Spec. ............................................................................352
Table 20-11. KBC AC Timing Spec. ..........................................................................................352
Table 20-12. USB Host AC Timing Spec. ..................................................................................352
Table 20-13. AFECK Clock Input AC Timing Spec. (PLL1 : bypass) .......................................352
Table 20-14. AFECK Clock Input AC Timing Spec. (PLL1 : operating) ...................................353
Table 20-15. UCK Clock Input AC Timing Spec. (PLL2 : bypass) ...........................................353
Table 20-16. UCK Clock Input AC Timing Spec. (PLL2 : operating) .......................................353
Figures
Figure 5-1. CPU Interface Module Interconnection Diagram......................................................44
Figure 5-2. Low-Speed Basic Internal Peripheral Bus Access Timing ........................................45
Содержание HD64465
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