Rev. 3.0, 03/01, page 74 of 390
7.3.3
Port Interrupt Control Register
This register is used to enable or disable to generate the interrupt request when an interrupt event is
triggered on each I/O port pin. An interrupt request is generated when an interrupt event is
triggered and its corresponding register bit is set to “1”. But the Interrupt request will not be
generated if its corresponding control register bit is “0,” despite that the interrupt event is triggered.
This register can independently select the trigger edge of the interrupt events on each I/O port pin.
GPAICR -- Address: H'10004020
Bit
15
14
13
12
11
10
9
8
Bit Name
PA7TS
PA6TS
PA5TS
PA4TS
PA3TS
PA2TS
PA1TS
PA0TS
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Bit Name
PA7IM
PA6IM
PA5IM
PA4IM
PA3IM
PA2IM
PA1IM
PA0IM
Initial Value
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
GPBICR -- Address: H'10004022
Bit
15
14
13
12
11
10
9
8
Bit Name
PB7TS
PB6TS
PB5TS
PB4TS
PB3TS
PB2TS
PB1TS
PB0TS
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Bit Name
PB7IM
PB6IM
PB5IM
PB4IM
PB3IM
PB2IM
PB1IM
PB0IM
Initial Value
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
GPCICR -- Address: H'10004024
Bit
15
14
13
12
11
10
9
8
Bit Name
PC7TS
PC6TS
PC5TS
PC4TS
PC3TS
PC2TS
PC1TS
PC0TS
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Содержание HD64465
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