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OwnershipChange Event
The OwnershipChange bit is set by the Host Controller when the Host Controller Driver sets the
OwnershipChangeRequest bit in the HcCommandStatus register. This ensures that an interrupt is
generated (unless it is masked) whenever ownership of the Host Controller is passed to and from
the operating system Host Controller Driver and any SMM-based Host Controller Driver in the
system. All interrupts resulting from an OwnershipChange event are not routable with the
InterruptRouting bit of the HcControl register and are delivered on the SMI pin only. If the Host
Controller does not implement an SMI pin, interrupts will not be generated at all on an
OwnershipChange event.
Host Controller Bus Master
The Host Controller Bus Master is the central block in the data path. It coordinates all access to the
PCI Interface.
There are two sources of bus mastering within USB Host Controller: the List Processor and the
Data Buffer Engine. The List Processor has control when it transfers Endpoint Descriptors,
Transfer Descriptors, and HCCA information. The List Processor gives control to the Data Buffer
Engine when the data pointed to by a Transfer Descriptor is to be transferred.
The Host Controller Bus Master consists of three main modules: The Bus Master Controller, the
Data Buffer Engine, and the Page Crossing Controller.
Bus Master Controller
The Bus Master Controller provides the PCI Interface (PCI IF) with the signals necessary to
perform PCI cycles on behalf of the Data Buffer Engine or List Processor. These signals are the
address of the first byte in the transfer, the size of the transfer in bytes, the direction of the transfer,
and the data for write cycles. The PCI IF will carry out the appropriate PCI cycle based on the
information provided.
In addition there are three control signals across the interface: a request signal from the Bus Master
Controller, and a cycle active and a data ready signal from the PCI Controller. The Bus Master
Controller requests access when it needs to transfer a cycle on the PCI Bus. The PCI IF arbitrates
internally to the ASIC for access to the PCI bus. (For USB Host Controller the arbitration is
immediate since it has no other PCI masters). When access is granted, the PCI IF asserts the cycle
active signal which remains asserted until the cycle completes. The PCI IF asserts the data ready
signal for one PCI period for each Dword transfer across the interface. On a write, the data ready
signal indicates that the PCI IF has consumed the Dword presented by the Bus Master Controller.
On a read, the data ready signal indicates that a valid Dword is present on the PCI read data bus.
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