Rev. 3.0, 03/01, page 142 of 390
(10) Rx Status Register (IRSR)
Address: H'1000710E (Bank 0, Read)
Bit
7
6
5
4
3
2
1
0
Bit Name
ABORT
CRCER
RFOVF
EOF
RFEM
SYNC
-
-
Initial Value
0
0
0
0
0
1
-
-
R/W
R
R
R
R
R
R
-
-
Bit
Description
Default
7
Abort Detect (ABORT)
When set to ‘1’, indicates abort sequence detected in the receive data stream of current
packet.
In 1Mbit mode, the abort sequence is characterized by seven or more consecutive 1 in the
data stream.
In 4Mbit mode, the abort sequence is represented by two (2) or more illegal symbols 0000
after a valid start flag but before a complete stop flag; or an illegal symbol, which is not
part of a valid stop flag field, received any time after a valid flag.
-
6
CRC or Alignment Error (CRCER)
When set to ‘1’, indicates a CRC or alignment error was detected in the incoming data
stream. This bit is automatically cleared upon detection of the beginning/start flag of the
next incoming packet.
-
5
RX FIFO Overflow (RFOVF)
When set to ‘1’, indicates the host system was not fast enough removing the data out of
Rx FIFO before it overflowed with receive data.
-
4
End of Frame (EOF)
End of Frame (EOF): When set to ‘1’, indicates an ending/stop flag or abort sequence was
detected in the incoming data stream. This bit is automatically cleared upon detection of
the beginning/start flag of the next incoming packet.
-
3
RX FIFO Empty (RFEM)
When set to ‘1,’ indicates Rx FIFO is not empty. When set to ‘0,’ indicates Rx FIFO is
empty. When this bit is set, it does not cause an interrupt; rather it is used to unload the
FIFO by polling.
Note: Rx FIFO Level (bit 7 of Rx Control Register) has no effect on the Rx Data Available
bit.
-
2
Sync/Hunt Status (SYNC)
When set to ‘1,’ indicates a transition or status change occurred on the internal Sync/Hunt
signal. The following conditions cause the Sync/Hunt signal to change states:
•
When Enter Hunt Mode command is issued
•
Valid SDLC start or stop flag is detected
•
Valid preamble or stop flag is detected (4Mbit mode)
If bit 3 of Rx Control Register (Enables Sync/Hunt Change Interrupt bit) is enabled, the
setting of Sync/Hunt Change bit causes an interrupt to the host system. Reading the Rx
Status Register after the interrupt has occurred clears the Sync/Hunt Change bit. If the bit
3 of Rx Control Register is disabled, reading Rx Status register will directly provide the
status of the Sync/Hunt signal and will not clear the Sync/Hunt Change bit.
-
1 - 0
Reserved
-
Содержание HD64465
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