Rev. 3.0, 03/01, page 134 of 390
11.2.3
Register Description
(1) Master Control Register (IMSTR)
Address: H'10007100 (Bank 0, 1, 2, Read/ Write)
Bit
7
6
5
4
3
2
1
0
Bit Name
IEN
TXEN
RXEN
BKSEL4 BKSEL3 BKSEL2 BKSEL1 BKSEL0
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Description
Default
7
FIR Interrupt Enable (IEN)
Setting this bit to 1 enables all FIR Controller interrupts.
0
6
Transmitter Enable (TXEN)
Setting this bit to 1 enables the transmitter logic in the FIR Controller. No packets are
transmitted until the transmitter has been enabled.
0
5
Receiver Enable (RXEN)
Setting this bit to 1 enables the receiver logic in the FIR Controller. No packets are
received until the receiver has been enabled.
0
4 - 0
Bank Select (BKSEL[4:0])
Bank# b4 b3 b2 b1 b0
Bank0 0 0 0 0 0
Bank1 0 0 0 0 1
Bank2 0 0 0 1 0
00000
Содержание HD64465
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