Rev. 3.0, 03/01, page 321 of 390
HcInterruptEnable
Writing a ‘1’ to a bit in this register sets the corresponding bit, while writing a ‘0’ to a bit leaves
the bit unchanged.
Table 18.27 HcInterrutpEnable Register
Register: HcInterruptEnable
Offset: 10-13
Bits
Reset
R/W
Description
31
0b
R/W
MasterInterruptEnable
This bit is a global interrupt enable. A write of ‘1’ allows
interrupts to be enabled via the specific enable bits listed
above.
30
0b
R/W
OwnershipChangeEnable
0: Ignore
1: Enable interrupt generation due to Ownership Change.
29 - 7
0h
-
Reserved. Read/Write 0's
6
0b
R/W
RootHubStatusChangeEnable
0: Ignore
1: Enable interrupt generation due to Root Hub Status Change.
5
0b
R/W
FrameNumberOverflowEnable
0: Ignore
1: Enable interrupt generation due to Frame Number Overflow.
4
0b
R/W
UnrecoverableErrorEnable
This event is not implemented. All writes to this bit will be
ignored.
3
0b
R/W
ResumeDetectedEnable
0: Ignore
1: Enable interrupt generation due to Resume Detected.
2
0b
R/W
StartOfFrameEnable
0: Ignore
1: Enable interrupt generation due to Start of Frame.
1
0b
R/W
WritebackDoneHeadEnable
0: Ignore
1: Enable interrupt generation due to Writeback Done Head.
0
0b
R/W
SchedulingOverrunEnable
0: Ignore
1: Enable interrupt generation due to Scheduling Overrun.
Содержание HD64465
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