Rev. 3.0, 03/01, page 169 of 390
12.8
FIFO Interrupt Mode Operation
(1) RCVR Interrupt
When bit 0 of UFCR and bit 0 of UIER are set to 1, the RCVR FIFO and receiver interrupts are
enabled. The RCVR interrupt occurs under the following conditions:
a. The receive data available interrupt and the UIIR, receive data available indication, will be
issued only if the FIFO has reached its programmed trigger level. They will be cleared as soon
as the FIFO drops below its trigger level.
b. The receiver line status interrupt has higher priority than the received data available interrupt.
c. The time-out timer will be reset after receiving a new character or after the Host reads the
RCVR FIFO whenever a time-out interrupt occurs. The timer will be reset when the Host reads
one character form the RCVR FIFO.
RCVR FIFO timer-out Interrupt: By enabling RCVR FIFO and receiver interrupts, the RCVR
FIFO time-out interrupt will occur under the following conditions:
a. It will occur only if there is at least one character in the FIFO whenever the period between the
most recent received serial character and the most recent Host read from the FIFO is longer
than four (4) consecutive character times.
b. The time-out timer will be reset after receiving a new character or after the Host reads the
RCVR FIFO whenever any time-out interrupt occurs. The timer will be reset when the Host
reads one character from the RCVR FIFO.
(2) XMIT Interrupt
By setting the bit 0 of UFCR and the bit 1 of UIER to high, the XMIT FIFO and transmitter
interrupts are enabled, and the XMIT interrupt will occur as follows:
a. The transmitter interrupt will occur when the XMIT FIFO is empty, and it will be reset if the
THR is written or the UIIR is read.
b. The transmitter FIFO empty indications will be delayed one character time minus the last stop
bit time whenever the following conditions occurs: THRE=1 and there have not been at least
two bytes in the transmitter FIFO at the same time since the last THRE=1. The transmitter
interrupt after changing the bit 0 of UFCR will be immediate. Once it is enabled, the THRE
indication is delayed 1 character time minus the last stop bit time.
The character time-out and RCVR FIFO trigger level interrupts are in the same priority order as
the received data available interrupt. The XMIT FIFO empty is in the same priority as the
transmitter holding register empty interrupt.
Содержание HD64465
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