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(3) Set Receiver Enable bit.
Set IEN and RXEN to enable FIR interrupt and Receiver. (Set a0h to IMSTCR)
(4) FIR mode logic detects Carrier, receive clock starts running. If consecutive ‘1’s are
received, the receive clock may not be synchronized with the incoming data.
T2: Flag(s)/Preambles Detection:
(1) When the Start flag is detected, all counters in the receiver are initialized. Characters can be
recognized from this point on.
(2) ‘0’ deletion starts for 1M-bit mode only.
T3: Address Matching:
(1) The first non-flag byte after the starting flag is the address. Depending on the address mode
option (RADM[1:0] in IRCR), the frame can be rejected or started for receiving. If the
frame is rejected, the receiver will look for the next Start flag and another address match.
T4: Data Receiving:
(1) When a data byte is received, the data and the three status bits are stored in the Rx FIFO.
(2) If DMA is enabled, DMA request is activated when the FIFO threshold level is reached.
DMA request continues until all data stored in the FIFO have been transferred to the host
receive buffer. However, the three status bits in the FIFO will not be transferred to the host.
(3) If DMA is not used, the READ Rx FIFO command can be used. (Read data from IRFR)
Read the status bits first, then read the data byte. If EOF or Abort is set to 1, the data byte
just read is the last byte of the packet. If the FIFO is still not empty, the next entry is the
beginning of another packet.
(4) Rx Byte Counter and Rx Ring Frame counter increase accordingly.
T5: Closing Flag:
(1) End Of Frame bit will be set when the closing flag is detected.
(2) CRC pattern is checked. Frame error is set if CRC is wrong.
Содержание HD64465
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