Rev. 3.0, 03/01, page 319 of 390
Table 18.24 HcControl Register (cont’d)
Register:
HcControl
Offset: 04-07
Bits
Reset
R/W
Description
2
0b
R/W
PeriodicListEnable
When set, this bit enables processing of the Periodic (interrupt
and isochronous) list. The Host Controller checks this bit prior
to attempting any periodic transfers in a frame.
1 - 0
00b
R/W
ControlBulkServiceRatio
Specifies the number of Control Endpoints serviced for every
Bulk Endpoint. Encoding is N-1 where N is the number of
Control Endpoints (i.e. ‘00’ = 1 Control Endpoint; ‘11’ = 3
Control Endpoints)
HccommandStatus
Table 18.25 HcCommandStatus Register
Register: HcCommandStatus
Offset: 08-0B
Bits
Reset
R/W
Description
31 - 18
0h
-
Reserved. Read/Write 0's
17 - 16
00b
ScheduleOverrunCount
This field increments every time the SchedulingOverrun bit in
HcInterruptStatus is set. The count wraps from ‘11’ to ‘00.’
15 - 4
0h
-
Reserved. Read/Write 0's
3
0b
R/W
OwnershipChangeRequest
When set by software, this bit sets the OwnershipChange field
in HcInterruptStatus. The bit is cleared by software.
2
0b
R/W
BulkListFilled
When set, this bit indicates there is an active ED on the Bulk
List. The bit may be set by either software or the Host
Controller. The bit is cleared by the Host Controller each time it
begins processing the head of the Bulk List.
1
0b
R/W
ControlListFilled
When set, this bit indicates there is an active ED on the Control
List. The bit may be set by either software or the Host
Controller. The bit is cleared by the Host Controller each time it
begins processing the head of the Control List.
0
0b
R/W
HostControllerReset
This bit is set to initiate a software reset. This bit is cleared by
the Host Controller upon completion of the reset operation.
Содержание HD64465
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