Rev. 3.0, 03/01, page 314 of 390
If the hub is suspended, i.e. U
SB
S
USPEND
, while the port is also suspended, the port does not
respond to a U
SB
R
ESUME
transition. However, an upstream resume at the port forces a
U
SB
R
ESUME
transition.
Interrupts
A Root Hub interrupt, RootHubStatusChange, is generated by setting any of the XXXXChange
fields in the HcRhStatus and HcRhPortStatus registers. Writing the change bit to '1' clears the
source of the interrupt.
Clock Generation
The USB interface is sourced by a 48 MHz clock which allows for a 4x data rate oversampling to
maintain the receiver phase lock. This clock also sources all USB related clock rates (12 MHz and
1.5 MHz).
Static SOF Clock
As the USB system host, the system frame counter is maintained at a constant 1 ms interval. This
requires a static 12 MHz clock. This is created by dividing down the 48 MHz internal clock
source. The clock is enabled when the HC is not in the U
SB
S
USPEND
state.
Data Rate Clock
The SIE requires that the transmit and receive clocks operate at 12 and 1.5 MHz. During FS
transmissions, the data rate clock is equivalent to the static 12 MHz SOF clock. When the SIE has
a LS packet the data rate clock must be changed to 1.5 MHz following the preamble token. The
1.5 MHz data rate is maintained until the response packet is concluded, if expected.
When receiving data, the data rate clock must match that of the source. Working in conjunction
with the phase lock circuitry, the data rate clock is adjusted to maintain a 1 to 1 ratio of data bits
and data clocks. This will result in periodic adjustment of the internal 48 MHz clock periods to
maintain synchronization with the data source. When the packet is complete the data rate clock is
re-linked to the static 12 MHz clock discussed above. For more information on the data receiver
see HC Register Summary section.
Содержание HD64465
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