Fuji Electric micrex-sx NP1F-MP1, Руководство пользователя, Страница: 125 / 250

5-70
5-3 I/O Area of NP1F-MP2
) d n a m m o c e g n a h c d e e p S : e m a n l a n g i S ( 5 t i B
<Description>
• In the pulse generation mode, while this signal is “1,” set value data is continuously written in the target frequency
register.
Set value data
(PC == > MP2)
Target frequency register
(internal register)
Speed change command
(PC == > MP2)
Speed changing
(PC <== MP2)
Speed 1 Speed 2 Speed 3
Speed 2 Speed 1 Speed 3 Speed 4
Not changed over to “speed 4” because
the speed change command is “0.”
“1”
“1”
For speed change, handshaking by response signal is not performed between the data write request and
response.
Precautions:
• In the pulse generation mode, with the combined module (MP1/MP2), addend data can be written in the command
pulse register, using the set value data area while speed is being changed by the speed change command.
This function is provided so that moving length data can be added and updated without stopping the operation for
changing speed from the PC.
The writing in the target frequency register uses 2 words of the set value data area and therefore is set after
stopping the processing for speed change.
(For details, refer to the paragraph for pulse count setting.)
Speed data (lower 16 bits) Lower word
Speed data
(upper 4 bits)
Upper word Pulse count data (12 bits)
Frequency
resolution For 20-bit structure (using the pulse count setting
buffer upper, middle and lower)
15 bit 0 bit
Speed data (16 bits)
Pulse count data (16 bits)
Lower word
Upper word
For 16-bit structure
(using the pulse count setting buffer 16) Frequency
resolution
15 bit 0 bit
While the speed change command is “1,” writing is disabled, except in the following registers.
Although the response signal to the write command is “1,” no data is updated.
Effective register: Pulse count setting buffer upper, middle and lower as well as buffer 16 register
• In position command mode, speed data cannot be set from the CPU module.
The data is automatically set in the target frequency register on the combined module (MP1/MP2) side.