8 CLOCK GENERATOR (CLG)
S1C17001 TECHNICAL MANUAL
EPSON
73
8.3 Peripheral Module Clock (PCLK) Control
The CLG module also controls the clock feed to peripheral modules.
The system clock is used unmodified for the peripheral module clock (PCLK).
Internal peripheral circuits
• Prescaler
• UART
• 8-bit timer
• 16-bit timer Ch.0 to 2
• Interrupt controller
• SPI
• I
2
C
• P port & port MUX
• PWM & capture timer
• MISC register
• Remote controller
• Control register for the
modules listed below
Clock
timer
Stopwatch
timer
Watchdog
timer
8-bit OSC1 timer
Gate
On/off control
PCLK
OSC3
OSC1
System clock
Figure 8.3.1: Peripheral module clock control circuit
Clock feed control
PCLK feed is controlled by PCKEN[1:0] (D[1:0]/CLG_PCLK register).
∗
PCKEN[1:0]
: PCLK Enable Bits in the PCLK Control (CLG_PCLK) Register (D[1:0]/0x5080)
Table 8.3.1: PCLK control
PCKEN[1:0]
PCLK feed
0x3
Permitted (on)
0x2
Setting prohibited
0x1
Setting prohibited
0x0
Prohibited (off)
(Default: 0x3)
The default setting is 0x3, which enables the clock feed. Stop the clock feed to reduce power consumption un-
less all peripheral modules (modules listed above) within the internal peripheral circuit area need to be running.
Note: Do not set PCKEN[1:0] (D[1:0]/CLG_PCLK register) to 0x2 or 0x1, since doing so will stop the
operation of certain peripheral modules.
Peripheral modules not operating on PCLK
With the exception of control register access, the clock timer, stopwatch timer, watchdog timer, and 8-bit OSC1
timer operate using the OSC1 division clock. Stopping the PCLK prevents read/write access to/from the control
register, but operation will continue.
Содержание S1C17001
Страница 1: ...Technical Manual S1C17001 CMOS 16 BIT SINGLE CHIP MICROCONTROLLER ...
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