EMR-5000
IM02602012E
Name
Description
Logic.LE33.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE33.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE34.Gate Out
Signal: Output of the logic gate
Logic.LE34.Timer Out
Signal: Timer Output
Logic.LE34.Out
Signal: Latched Output (Q)
Logic.LE34.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE34.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE34.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE34.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE34.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE34.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE35.Gate Out
Signal: Output of the logic gate
Logic.LE35.Timer Out
Signal: Timer Output
Logic.LE35.Out
Signal: Latched Output (Q)
Logic.LE35.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE35.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE35.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE35.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE35.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE35.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE36.Gate Out
Signal: Output of the logic gate
Logic.LE36.Timer Out
Signal: Timer Output
Logic.LE36.Out
Signal: Latched Output (Q)
Logic.LE36.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE36.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE36.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE36.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE36.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE36.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE37.Gate Out
Signal: Output of the logic gate
Logic.LE37.Timer Out
Signal: Timer Output
Logic.LE37.Out
Signal: Latched Output (Q)
Logic.LE37.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE37.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE37.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE37.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE37.Gate In4-I
State of the module input: Assignment of the Input Signal
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Содержание EMR-5000
Страница 62: ...EMR 5000 IM02602012E Ethernet RJ45 Terminal Marking www eaton com 62 1 8 TxD TxD RxD N C N C RxD N C N C...
Страница 271: ...EMR 5000 IM02602012E Fault Recorder Module Signals Signal Description Res record Signal Delete Record www eaton com 271...
Страница 524: ...EMR 5000 IM02602012E Motor Protection Curves Motor Protection Curve Example 1 www eaton com 524...
Страница 525: ...EMR 5000 IM02602012E Motor Protection Curve Example 2 without RTDs www eaton com 525...
Страница 526: ...EMR 5000 IM02602012E Motor Protection Curve Example 3 with RTDs www eaton com 526...
Страница 930: ...EMR 5000 IM02602012E Real Time Clock Running Reserve of the Real Time Clock 1 year min www eaton com 930...
