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EMR-5000
IM02602012E
Name
Description
Logic.LE9.Timer Out
Signal: Timer Output
Logic.LE9.Out
Signal: Latched Output (Q)
Logic.LE9.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE9.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE9.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE9.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE9.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE9.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE10.Gate Out
Signal: Output of the logic gate
Logic.LE10.Timer Out
Signal: Timer Output
Logic.LE10.Out
Signal: Latched Output (Q)
Logic.LE10.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE10.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE10.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE10.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE10.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE10.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE11.Gate Out
Signal: Output of the logic gate
Logic.LE11.Timer Out
Signal: Timer Output
Logic.LE11.Out
Signal: Latched Output (Q)
Logic.LE11.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE11.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE11.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE11.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE11.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE11.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE12.Gate Out
Signal: Output of the logic gate
Logic.LE12.Timer Out
Signal: Timer Output
Logic.LE12.Out
Signal: Latched Output (Q)
Logic.LE12.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE12.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE12.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE12.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE12.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE12.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE13.Gate Out
Signal: Output of the logic gate
Logic.LE13.Timer Out
Signal: Timer Output
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1038
Содержание EMR-5000
Страница 62: ...EMR 5000 IM02602012E Ethernet RJ45 Terminal Marking www eaton com 62 1 8 TxD TxD RxD N C N C RxD N C N C...
Страница 271: ...EMR 5000 IM02602012E Fault Recorder Module Signals Signal Description Res record Signal Delete Record www eaton com 271...
Страница 524: ...EMR 5000 IM02602012E Motor Protection Curves Motor Protection Curve Example 1 www eaton com 524...
Страница 525: ...EMR 5000 IM02602012E Motor Protection Curve Example 2 without RTDs www eaton com 525...
Страница 526: ...EMR 5000 IM02602012E Motor Protection Curve Example 3 with RTDs www eaton com 526...
Страница 930: ...EMR 5000 IM02602012E Real Time Clock Running Reserve of the Real Time Clock 1 year min www eaton com 930...