5. Memory organization
A96G140/A96G148/A96A148 User’s manual
42
Table 5. SFR Map (continued)
Address Function
Symbol
R/W
@Reset
7
6
5
4
3
2
1
0
C0H
External Interrupt Flag 0 Register
EIFLAG0
R/W
0
0
0
0
0
0
0
0
C1H
P3 Direction Register
P3IO
R/W
0
0
0
0
0
0
0
0
C2H
Timer 2 Control Low Register
T2CRL
R/W
0
0
0
0
–
0
–
0
C3H
Timer 2 Control High Register
T2CRH
R/W
0
–
0
0
–
–
–
0
C4H
Timer 2 A Data Low Register
T2ADRL
R/W
1
1
1
1
1
1
1
1
C5H
Timer 2 A Data High Register
T2ADRH
R/W
1
1
1
1
1
1
1
1
C6H
Timer 2 B Data Low Register
T2BDRL
R/W
1
1
1
1
1
1
1
1
C7H
Timer 2 B Data High Register
T2BDRH
R/W
1
1
1
1
1
1
1
1
C8H
Oscillator Control Register
OSCCR
R/W
–
0
1
0
1
0
0
0
C9H
P4 Direction Register
P4IO
R/W
0
0
0
0
0
0
0
0
CBH
USART Control Register 1
UCTRL1
R/W
0
0
0
0
0
0
0
0
CCH
USART Control Register 2
UCTRL2
R/W
0
0
0
0
0
0
0
0
CDH
USART Control Register 3
UCTRL3
R/W
0
0
0
0
–
0
0
0
CFH
USART Status Register
USTAT
R/W
1
0
0
0
0
0
0
0
D0H
Program Status Word Register
PSW
R/W
0
0
0
0
0
0
0
0
D1H
P5 Direction Register
P5IO
R/W
–
–
0
0
0
0
0
0
D2H
P0 Function Selection Low Register
P0FSRL
R/W
0
0
0
0
0
0
0
0
D3H
P0 Function Selection High Register
P0FSRH
R/W
0
0
0
0
0
0
0
0
D4H
P1 Function Selection Low Register
P1FSRL
R/W
0
0
0
0
0
0
0
0
D5H
P1 Function Selection High Register
P1FSRH
R/W
0
0
0
0
0
0
0
0
D6H
P2 Function Selection Register
P2FSR
R/W
–
–
–
0
0
0
0
0
D8H
Low Voltage Reset Control Register
LVRCR
R/W
–
–
–
0
0
0
0
0
D9H
USI0 Control Register 1
USI0CR1
R/W
0
0
0
0
0
0
0
0
DAH
USI0 Control Register 2
USI0CR2
R/W
0
0
0
0
0
0
0
0
DBH
USI0 Control Register 3
USI0CR3
R/W
0
0
0
0
0
0
0
0
DCH
USI0 Control Register 4
USI0CR4
R/W
0
–
–
0
0
–
0
0
DDH
USI0 Slave Address Register
USI0SAR
R/W
0
0
0
0
0
0
0
0
DEH
P0 De-bounce Enable Register
P0DB
R/W
0
0
0
0
0
0
0
0
DFH
P1/P5 De-bounce Enable Register
P15DB
R/W
–
–
0
0
0
0
0
0