12. Timer 0/1/2/3/4/5
A96G140/A96G148/A96A148 User’s manual
132
The timer/counter 4 can be a divided clock of a system clock selected from prescaler output and T3 A
Match (timer 3 A match signal). The clock source is selected by a clock selection logic controlled by
clock selection bits (T4CK[2:0]).
TIMER 4 clock source: fX/1, fX/2, fX/4, fX/8, fX/32, fX/128, fX/512 and T3 A Match
In capture mode, data is captured into input capture data registers (T4BDRH/T4BDRL) by EINT4. In
timer/counter mode, whenever counter value is equal to T4ADRH/L, T4O port toggles. In addition, the
TIMER 4 outputs PWM waveform to PWM4O port in the PPG mode.
Table 22. TIMER 4 Operating Modes
T4EN
P0FSRH[3:2]
T4MS[1:0]
T4CK[2:0]
Timer 4
1
11
00
XXX
16 Bit Timer/Counter Mode
1
00
01
XXX
16 Bit Capture Mode
1
11
10
XXX
16 Bit PPG Mode(one-shot mode)
1
11
11
XXX
16 Bit PPG Mode(repeat mode)
12.5.1
16-bit timer/counter mode
16-bit timer/counter mode is selected by control registers, and the 16-bit timer/counter has counter
registers and data registers as shown in figure 60. The counter register is increased by internal or timer
4 A match clock input.
Timer 4 can use the input clock with one of 1, 2, 4, 8, 32, 128, 512 and T3 A Match prescaler division
rates (T4CK[2:0]). When the values of T4CNTH/T4CNTL and T4ADRH/T4ADRL are identical to each
other in timer 4, a match signal is generated and the interrupt of Timer 4 occurs. The T4CNTH/T4CNTL
values are automatically cleared by the match signal. It can be cleared by software (T4CC) too.
