16. USART 2
A96G140/A96G148/A96A148 User’s manual
202
Internally, after receiving the first stop bit, the Receiver is in idle state and waiting to find start bit.
Figure 106. Sampling of Data and Parity Bit
A process for detecting stop bit is similar to the clock and data recovery process. That is, if 2 or more
samples of 3 center values have high level, correct stop bit is detected. If not, a Frame Error flag will be
set. After deciding whether a valid stop bit is received or not, the Receiver enters into idle state and
monitors the RXD2 line to check a valid high to low transition is detected (start bit detection).
Figure 107. Stop Bit Sampling and Next Start Bit Sampling
16.9
SPI mode
The USART2 can be set to operate in industrial standard SPI compliant mode. The SPI mode has the
following features.
Full duplex, three-wire synchronous data transfer
Master or Slave operation
Supports all four SPI modes of operation (mode0, 1, 2, and 3)
Selectable LSB first or MSB first data transfer
Double buffered transmit and receive
Programmable transmit bit rate
When SPI mode is enabled (UMSEL[1:0]=3), the Slave Select (SS2) pin becomes active low input in
slave mode operation, or can be output in master mode operation if SPISS bit is set.
RxD2
1
2
3
4
5
6
7
8
9
10
11
12 13
14 15
16
1
BIT n
1
2
3
4
5
6
7
8
1
Sample
(U2X = 0)
Sample
(U2X = 1)
RxD2
1
2
3
4
5
6
7
8
9
10
11
12 13
STOP 1
1
2
3
4
5
6
7
Sample
(U2X = 0)
Sample
(U2X = 1)
(A)
(B)
(C)
