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In this demo, the accelerometer is controlled through a 3-wire SPI. Before reading any data from the
accelerometer, the controller sets 1 on the SPI bit in the Register 0x31 – DATA_FORMAT register.
The 3-wire SPI Controller block reads the digital accelerometer X-axis value, to determine the tilt
of the board. The LEDs are lit up as if they were a bubble, floating to the top of the board.
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Project directory: DE0_NANO_GSensor
Bit stream used: DE0_NANO_G_Sensor.sof
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Demo Batch File Folder: DE0_NANO_GSensor\demo_batch
The demo batch file includes the following files:
FPGA Configure File: DE0_NANO_G_Sensor.sof
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Make sure Quartus II is installed on your PC.
Connect USB cable to the DE0-Nano board and install the USB Blaster driver if necessary.
Execute the demo batch file “test.bat” under the batch file folder,
DE0_NANO_GSensor
\
demo_batch
. This will load the demo into the FPGA.
Tilt the DE0-Nano board from side to side and observe the result on the LEDs.
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Many applications use SDRAM to provide temporary storage. In this demonstration hardware and
software designs are provided to illustrate how to perform memory access in QSYS. We describe
how the Altera’s SDRAM Controller IP is used to access a SDRAM, and how the Nios II processor
is used to read and write the SDRAM for hardware verification. The SDRAM controller handles the
complex aspects of using SDRAM by initializing the memory devices, managing SDRAM banks,
and keeping the devices refreshed at appropriate intervals.
System Block Diagram
Figure 8-15
shows the system block diagram of this demonstration. The system requires a 50 MHz
Summary of Contents for De0-Nano
Page 1: ...1 ...
Page 4: ...4 9 3 Revision History 155 9 4 Copyright Statement 155 ...
Page 44: ...44 Figure 6 5 Browse to find the location Figure 6 6 There is no need to test the driver ...
Page 90: ...90 Figure 7 14 Add NIOS II Processor ...
Page 93: ...93 Figure 7 17 Rename the CPU 1 Figure 7 18 Rename the CPU 2 ...
Page 98: ...98 Figure 7 23 Add On Chip Memory ...
Page 100: ...100 Figure 7 25 Update Total memory size ...
Page 102: ...102 Figure 7 28 Update CPU settings ...
Page 104: ...104 Figure 7 30 Add PIO ...
Page 106: ...106 Figure 7 32 PIO 21 Rename pio_0 to pio_led as shown in Figure 7 33 Figure 7 33 Rename PIO ...
Page 113: ...113 Figure 7 43 Input verilog Text Figure 7 44 Open DE0_NANO_SOPC v ...
Page 146: ...146 Figure 8 16 Display Progress and Result Information for the SDRAM Demonstration ...
Page 150: ...150 Figure 9 3 Select Devices Page ...
Page 151: ...151 Figure 9 4 Convert Programming Files Page ...
