34
Chapter 5
DE0-Nano System Builder
This chapter describes how users can create a custom design project on the DE0-Nano board by
using DE0-Nano Tool – DE0-Nano System Builder.
5
5
.
.
1
1
I
I
n
n
t
t
r
r
o
o
d
d
u
u
c
c
t
t
i
i
o
o
n
n
The DE0-Nano System Builder is a Windows based software utility, designed to assist users in
creating a Quartus II project for the DE0-Nano board within minutes. The generated Quartus II
project files include:
Quartus II Project File (.qpf)
Quartus II Setting File (.qsf)
Top-Level Design File (.v)
Synopsys Design Constraints file (.sdc)
Pin Assignment Document (.htm)
By providing the above files, DE0-Nano System Builder helps to prevents occurrence of situations
that are prone to errors when users manually edit the top-level design file or place pin assignments.
The common mistakes that users encounter are the following:
1. Board damaged for wrong pin/bank voltage assignments.
2. Board malfunction caused by wrong device connections or missing pin counts for connected
ends.
3. Performance degeneration because of improper pin assignments.
5
5
.
.
2
2
G
G
e
e
n
n
e
e
r
r
a
a
l
l
D
D
e
e
s
s
i
i
g
g
n
n
F
F
l
l
o
o
w
w
This section will introduce the general design flow to build a project for the DE0-Nano board via
the DE0-Nano System Builder. The general design flow is illustrated in
Figure 5-1
.
To create a new system using the DE0-Nano System Builder, begin by launching the DE0-Nano
System Builder software. The software will then prompt you to specify the name of the project you
wish to create, as well as the components on the DE0-Nano board you wish to you. Once your
specification is complete, you can generate the system.
Summary of Contents for De0-Nano
Page 1: ...1 ...
Page 4: ...4 9 3 Revision History 155 9 4 Copyright Statement 155 ...
Page 44: ...44 Figure 6 5 Browse to find the location Figure 6 6 There is no need to test the driver ...
Page 90: ...90 Figure 7 14 Add NIOS II Processor ...
Page 93: ...93 Figure 7 17 Rename the CPU 1 Figure 7 18 Rename the CPU 2 ...
Page 98: ...98 Figure 7 23 Add On Chip Memory ...
Page 100: ...100 Figure 7 25 Update Total memory size ...
Page 102: ...102 Figure 7 28 Update CPU settings ...
Page 104: ...104 Figure 7 30 Add PIO ...
Page 106: ...106 Figure 7 32 PIO 21 Rename pio_0 to pio_led as shown in Figure 7 33 Figure 7 33 Rename PIO ...
Page 113: ...113 Figure 7 43 Input verilog Text Figure 7 44 Open DE0_NANO_SOPC v ...
Page 146: ...146 Figure 8 16 Display Progress and Result Information for the SDRAM Demonstration ...
Page 150: ...150 Figure 9 3 Select Devices Page ...
Page 151: ...151 Figure 9 4 Convert Programming Files Page ...