Terasic De0-Nano, User Manual

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Figure 6-42 Completed Pin Planning Example
Now, you are finished creating your Quartus II design!
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Timing settings are critically important for a successful design. For this tutorial you will create a
basic Synopsys Design Constraints File (.sdc) that the Quartus II TimeQuest Timing Analyzer uses
during design compilation. For more complex designs, you will need to consider the timing
requirements more carefully.
To create an SDC, perform the following steps:
1. Open the TimeQuest Timing Analyzer by choosing Tools > TimeQuest Timing Analyzer .
2. Select File > New SDC file . The SDC editor opens.
3. Type the following code into the editor:
create_clock -period 20.000 -name CLOCK_50
derive_pll_clocks
derive_clock_uncertainty
4. Save this file as my_first_fpga.sdc (see Figure 6-43 )