Terasic De0-Nano, User Manual

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Chapter 6
Tutorial: Creating an FPGA Project
This tutorial provides comprehensive information for understanding how to create a FPGA design
and run it on the DE0-Nano development and education board. The following sections provide a
quick overview of the design flow, explaining what is needed to get started, and describe what is
taught in this tutorial.
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Figure 6-1 shows a block diagram of the FPGA design flow.
The first step in the FPGA design flow starts is design entry. The standard design entry methods are
using schematics or a hardware description language (HDL), such as Verilog HDL or VHDL. The
design entry step is where the designer creates the digital circuit to be implemented inside the
FPGA. The flow then proceeds through compilation, simulation, programming, and verification in
the FPGA hardware.
Figure 6-1 Design Flow
This tutorial describes all of the steps except for simulation. Although it is not covered in this
document, simulation is very important to learn. There are two types of simulation, Functional and
Timing Functional simulation allows you to verify that your hardware is performing the desired
functionality. Timing (or post place-and-route) simulation verifies that the design meets timing and
functions appropriately in the device. Simulation tutorials can be found on the Altera University
Program website at http://university.altera.com.