Terasic De0-Nano User Manual Download Page 53

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always @ (posedge CLOCK_5) // on positive clock edge

begin

counter_out <= count 1;// increment counter

end

endmodule // end of module counter

Figure 6-15 The Verilog File of simple_counter.v

5. Save the file by choosing

File > Save

, pressing

Ctrl + S

, or by clicking the floppy disk icon.

6. Select

File > Create/Update > Create Symbol Files for Current File

to convert the

simple_counter.v

file to a Symbol File (.sym). You will use this Symbol File to add the HDL code

to your schematic.

The Quartus II software creates a Symbol File and displays a message (see

Figure 6-16

Figure 6-16 Create Symbol File was Successful

7. Click

8. To add the

simple_counter.v

symbol to the top-level design, click the

my_first_fpga.bdf

tab.

Summary of Contents for De0-Nano

Page 1: ...1 ...

Page 2: ... 3 2 General User Input Output 12 3 3 SDRAM Memory 15 3 4 I2C Serial EEPROM 16 3 5 Expansion Headers 17 3 6 A D Converter and 2x13 Header 20 3 7 Digital Accelerometer 23 3 8 Clock Circuitry 23 3 9 Power Supply 24 CHAPTER 4 DE0 NANO CONTROL PANEL 26 4 1 Control Panel Setup 26 4 2 Controlling the LEDs 28 4 3 Switches and Pushbuttons 28 4 4 Memory Controller 29 4 5 Digital Accelerometer 31 4 6 ADC 32...

Page 3: ...OS II PROJECT 82 7 1 Required Features 82 7 2 Creation of Hardware Design 82 7 3 Download the Hardware Design 117 7 4 Create a hello_world Example Project 120 7 5 Build and Run the Program 123 7 6 Edit and Re Run the Program 124 7 7 Why the LED Blinks 126 7 8 Debugging the Application 127 7 9 Configure System Library 128 CHAPTER 8 DE0 NANO DEMONSTRATIONS 130 8 1 System Requirements 130 8 2 Breathi...

Page 4: ...4 9 3 Revision History 155 9 4 Copyright Statement 155 ...

Page 5: ... Nano includes a National Semiconductor 8 channel 12 bit A D converter and it also features an Analog Devices 13 bit 3 axis accelerometer device The DE0 Nano board includes a built in USB Blaster for FPGA programming and the board can be powered either from this USB port or by an external power source The board includes expansion headers that can be used to attach various Terasic daughter cards or...

Page 6: ...r pins two 3 3V power pins and four ground pins Memory devices o 32MB SDRAM o 2Kb I2C EEPROM General user input output o 8 green LEDs o 2 debounced pushbuttons o 4 position DIP switch G Sensor o ADI ADXL345 3 axis accelerometer with high resolution 13 bit A D Converter o NS ADC128S022 8 Channel 12 bit A D Converter o 50 Ksps to 200 Ksps Clock system o On board 50MHz clock oscillator Power Supply o...

Page 7: ...h includes component datasheets demonstrations schematic and user manual Figure 1 2 shows the photograph of the DE0 Nano kit contents Figure 1 2 DE0 Nano kit package contents 1 1 3 3 G Ge et tt ti in ng g H He el lp p Here is information of how to get help if you encounter any problem Terasic Technologies Tel 886 3 575 0880 Email support terasic com Altera Corporation Email university altera com ...

Page 8: ...ram and components 2 2 1 1 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s The picture of the DE0 Nano board is shown in Figure 2 1 and Figure 2 2 It depicts the layout of the board and indicates the locations of the connectors and key components Figure 2 1 The DE0 Nano Board PCB and component diagram top view ...

Page 9: ...f t th he e D DE E0 0 N Na an no o B Bo oa ar rd d Figure 2 3 shows the block diagram of the DE0 Nano board To provide maximum flexibility for the user all connections are made through the Cyclone IV FPGA device Thus the user can configure the FPGA to implement any system design Figure 2 3 Block diagram of DE0 Nano Board ...

Page 10: ... board two options are available which are described below 1 Connect a USB Mini B cable between a USB Type A host port and the board For communication between the host and the DE0 Nano board it is necessary to install the Altera USB Blaster driver software 2 Alternatively users can power up the DE0 Nano board by supplying 5V to the two DC 5 VCC5 pins of the GPIO headers or supplying 3 6 5 7V to th...

Page 11: ...GA can now be programmed through the Quartus II Programmer by selecting a configuration bit stream file with the sof filename extension Configuring the Spansion EPCS64 device The DE0 Nano board contains a Spansion EPCS64 serial configuration device This device provides non volatile storage of the configuration bit stream so that the information is retained even when the power supply to the DE0 Nan...

Page 12: ...re 3 2 JTAG Chain 3 3 2 2 G Ge en ne er ra al l U Us se er r I In np pu ut t O Ou ut tp pu ut t Pushbuttons The DE0 Nano board contains two pushbuttons shown in Figure 3 3 Each pushbutton is debounced using a Schmitt Trigger circuit as indicated in Figure 3 4 The two outputs called KEY0 and KEY1 of the Schmitt Trigger devices are connected directly to the Cyclone IV E FPGA Each pushbutton provides...

Page 13: ... LEDs There are 8 green user controllable LEDs on the DE0 Nano board The eight LEDs which are presented in Figure 3 4 allow users to display status and debugging information Each LED is driven directly by the Cyclone IV E FPGA Each LED is driven directly by a pin on the Cyclone IV E FPGA driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off ...

Page 14: ...ssignments for Push buttons Signal Name FPGA Pin No Description I O Standard KEY 0 PIN_J15 Push button 0 3 3V KEY 1 PIN_E1 Push button 1 3 3V Table 3 2 Pin Assignments for LEDs Signal Name FPGA Pin No Description I O Standard LED 0 PIN_A15 LED Green 0 3 3V LED 1 PIN_A13 LED Green 1 3 3V LED 2 PIN_B13 LED Green 2 3 3V LED 3 PIN_A11 LED Green 3 3 3V LED 4 PIN_D1 LED Green 4 3 3V LED 5 PIN_F3 LED Gre...

Page 15: ...e edge of the clock signal DRAM_CLK Connections between the FPGA and SDRAM chips are shown in Figure 3 6 Figure 3 6 Connections between FPGA and SDRAM Table 3 4 SDRAM Pin Assignments Signal Name FPGA Pin No Description I O Standard DRAM_ADDR 0 PIN_P2 SDRAM Address 0 3 3V DRAM_ADDR 1 PIN_N5 SDRAM Address 1 3 3V DRAM_ADDR 2 PIN_N6 SDRAM Address 2 3 3V DRAM_ADDR 3 PIN_M8 SDRAM Address 3 3 3V DRAM_ADD...

Page 16: ...a 15 3 3V DRAM_BA 0 PIN_M7 SDRAM Bank Address 0 3 3V DRAM_BA 1 PIN_M6 SDRAM Bank Address 1 3 3V DRAM_DQM 0 PIN_R6 SDRAM byte Data Mask 0 3 3V DRAM_DQM 1 PIN_T5 SDRAM byte Data Mask 1 3 3V DRAM_RAS_N PIN_L2 SDRAM Row Address Strobe 3 3V DRAM_CAS_N PIN_L1 SDRAM Column Address Strobe 3 3V DRAM_CKE PIN_L7 SDRAM Clock Enable 3 3V DRAM_CLK PIN_R4 SDRAM Clock 3 3V DRAM_WE_N PIN_C2 SDRAM Write Enable 3 3V...

Page 17: ...IN_F2 EEPROM clock 3 3V I2C_SDAT PIN_F1 EEPROM data 3 3V 3 3 5 5 E Ex xp pa an ns si io on n H He ea ad de er rs s The DE0 Nano board provides two 40 pin expansion headers Each header connects directly to 36 pins of the Cyclone IV E FPGA and also provides DC 5V VCC5 DC 3 3V VCC33 and two GND pins Figure 3 8 shows the I O distribution of the GPIO connectors ...

Page 18: ...sion headers Figure 3 9 Pin1 locations of the GPIO expansion headers Table 3 6 GPIO 0 Pin Assignments Signal Name FPGA Pin No Description I O Standard GPIO_0_IN0 PIN_A8 GPIO Connection DATA 3 3V GPIO_00 PIN_D3 GPIO Connection DATA 3 3V GPIO_0_IN1 PIN_B8 GPIO Connection DATA 3 3V GPIO_01 PIN_C3 GPIO Connection DATA 3 3V ...

Page 19: ...DATA 3 3V GPIO_021 PIN_F8 GPIO Connection DATA 3 3V GPIO_022 PIN_F9 GPIO Connection DATA 3 3V GPIO_023 PIN_E9 GPIO Connection DATA 3 3V GPIO_024 PIN_C9 GPIO Connection DATA 3 3V GPIO_025 PIN_D9 GPIO Connection DATA 3 3V GPIO_026 PIN_E11 GPIO Connection DATA 3 3V GPIO_027 PIN_E10 GPIO Connection DATA 3 3V GPIO_028 PIN_C11 GPIO Connection DATA 3 3V GPIO_029 PIN_B11 GPIO Connection DATA 3 3V GPIO_030...

Page 20: ...PIN_L14 GPIO Connection DATA 3 3V GPIO_127 PIN_N14 GPIO Connection DATA 3 3V GPIO_128 PIN_M10 GPIO Connection DATA 3 3V GPIO_129 PIN_L13 GPIO Connection DATA 3 3V GPIO_130 PIN_J16 GPIO Connection DATA 3 3V GPIO_131 PIN_K15 GPIO Connection DATA 3 3V GPIO_132 PIN_J13 GPIO Connection DATA 3 3V GPIO_133 PIN_J14 GPIO Connection DATA 3 3V 3 3 6 6 A A D D C Co on nv ve er rt te er r a an nd d 2 2x x1 13 ...

Page 21: ...ion of the 2x13 Header Figure 3 11 shows the connections on the 2x13 header A D converter and Cyclone IV device Figure 3 11 Wiring for 2x13 header and A D converter The pictures below indicate the pin 1 location of the 2x13 header ...

Page 22: ...ion DATA 6 3 3V GPIO_2 7 PIN_D14 GPIO Connection DATA 7 3 3V GPIO_2 8 PIN_F15 GPIO Connection DATA 8 3 3V GPIO_2 9 PIN_F16 GPIO Connection DATA 9 3 3V GPIO_2 10 PIN_F14 GPIO Connection DATA 10 3 3V GPIO_2 11 PIN_G16 GPIO Connection DATA 11 3 3V GPIO_2 12 PIN_G15 GPIO Connection DATA 12 3 3V GPIO_2_IN 0 PIN_E15 GPIO Input 3 3V GPIO_2_IN 1 PIN_E16 GPIO Input 3 3V GPIO_2_IN 2 PIN_M16 GPIO Input 3 3V ...

Page 23: ...lution at 16g SPI 3 wire or I2C 2 wire digital interface Flexible interrupts modes Figure 3 13 shows the connections between the ADXL345 and the Cyclone IV E device Figure 3 13 Wiring between the ADXL345 and the Cyclone IV E device Table 3 10 Pin Assignments for Digital Accelerometer Signal Name FPGA Pin No Description I O Standard I2C_SCLK PIN_F2 EEPROM clock 3 3V I2C_SDAT PIN_F1 EEPROM data 3 3V...

Page 24: ...vided through the USB 5V power the 5V VCC pins on the two 40 pin headers or the 2 pin power header The DC voltage is then stepped down to various required voltages For portable project applications connect a battery power supply 3 6 5 7V to the 2 pin external power header shown in Figure 3 15 Figure 3 15 Portable Battery Connection ...

Page 25: ...25 Power Distribution System Figure 3 16 shows the power distribution system on the DE0 Nano board Figure 3 16 DE0 Nano Power Distribution System ...

Page 26: ...ill attempt to download a configuration file onto the DE0 Nano board The configuration file contains a design that communicates with the peripheral devices on the board that are attached to the FPGA device Perform the following steps to ensure that the control panel starts up successfully 1 Make sure Quartus II 10 0 or later version is installed successfully on your PC 2 Connect a USB A to Mini B ...

Page 27: ...lustrated in Figure 4 2 The Control Circuit that performs the control functions is implemented in the FPGA board It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical interface is used to issue commands to the control circuit It handles all requests and performs data transfers between the computer and the DE0 Nano board Figure 4 2...

Page 28: ...sing the LED tab displays the window in Figure 4 3 Here you can directly turn the LEDs on or off individually or by clicking Light All or Unlight All Figure 4 3 Controlling LEDs 4 4 3 3 S Sw wi it tc ch he es s a an nd d P Pu us sh hb bu ut tt to on ns s Choosing the Switches tab displays the window in Figure 4 4 The function is designed to monitor the status of slide switches and pushbuttons in r...

Page 29: ...tches are functioning correctly Thus it can be used for troubleshooting purposes 4 4 4 4 M Me em mo or ry y C Co on nt tr ro ol ll le er r The Control Panel can be used to write read data to from the SDRAM EEPROM EPCS on the DE0 Nano board As an example we will describe how the SDRAM may be accessed the same approach is used to access the EEPROM and EPCS Click on the Memory tab and select SDRAM to...

Page 30: ...If the entire file is to be loaded then a checkmark may be placed in the File Length box instead of giving the number of bytes 3 To initiate the writing process click on the Write a File to Memory button 4 When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in the usual manner The Control Panel also supports loading files with a ...

Page 31: ...gi it ta al l A Ac cc ce el le er ro om me et te er r The Control Panel can be used to display the status of the Digital Accelerometer where it measures the output of its 3 axis X Y Z The measurement range and resolution is set to default value 2g acceleration of gravity and 10bit twos complement respectively Figure 4 6 shows the current digital accelerometer status of the DE0 Nano when Accelerome...

Page 32: ...ight channel 12 bit analog to digital converter reading The values shown are the ADC register outputs from all of the eight separate channels The voltage shown is the voltage reading from the separate pins on the extension header Figure 4 7 shows the ADC readings when the ADC tab is chosen Figure 4 7 ADC Readings ...

Page 33: ...emented in Verilog HDL code with SOPC builder The source code is not available on the DE0 Nano System CD To run the Control Panel users should make the configuration according to Section 4 1 Figure 4 8 depicts the structure of the Control Panel Each input output device is controlled by the Nios II Processor instantiated in the FPGA chip The communication with the PC is done via the USB Blaster lin...

Page 34: ...anually edit the top level design file or place pin assignments The common mistakes that users encounter are the following 1 Board damaged for wrong pin bank voltage assignments 2 Board malfunction caused by wrong device connections or missing pin counts for connected ends 3 Performance degeneration because of improper pin assignments 5 5 2 2 G Ge en ne er ra al l D De es si ig gn n F Fl lo ow w T...

Page 35: ...d an HTML file with pin descriptions will be generated as well To proceed with your design open the Quartus II CAD software and open your newly created project You will now be able to implement the logic of your design by describing your design in a hardware description language and connecting it to I Os in the top level wrapper file Once your design is complete compile the design using Quartus II...

Page 36: ...ystemBuilder on the DE0 Nano System CD Users can copy the whole folder to a host computer without installing the utility Launch the DE0 Nano System Builder by executing the DE0_NANO_SystemBuilder exe on the host computer and the GUI window will appear as shown in Figure 5 2 Figure 5 2 The DE0 Nano System Builder window Input Project Name Input project name as show in Figure 5 3 Project Name Type i...

Page 37: ... 4 Each component of the DE0 Nano is listed where users can enable or disable a component according to their design by simply marking a check or removing the check in the field provided If the component is enabled the DE0 Nano System Builder will automatically generate the associated pin assignments including the pin name pin location pin direction and I O standard Figure 5 4 System Configuration ...

Page 38: ...O Default followed by changing the pin name and pin direction according to the specification of the customized daughter board Figure 5 5 GPIO Expansion Group The Prefix Name is an optional feature which denotes the prefix pin name of the daughter card assigned in your design Users may leave this field empty Project Setting Management The DE0 Nano System Builder also provides functions to restore d...

Page 39: ...by DE0 Nano System Builder No Filename Description 1 Project name v Top level Verilog HDL file for Quartus II 2 Project name qpf Quartus II Project File 3 Project name qsf Quartus II Setting File 4 Project name sdc Synopsys Design Constraints file for Quartus II 5 Project name htm Pin Assignment Document Users can use Quartus II software to add custom logic into the project and compile the project...

Page 40: ...uage HDL such as Verilog HDL or VHDL The design entry step is where the designer creates the digital circuit to be implemented inside the FPGA The flow then proceeds through compilation simulation programming and verification in the FPGA hardware Figure 6 1 Design Flow This tutorial describes all of the steps except for simulation Although it is not covered in this document simulation is very impo...

Page 41: ... board helps you to verify whether your design is really working You have gone through the quick start guide and or the getting started user guide for your development kit These documents ensure that you have Installed the required software Determined that the development board functions properly and is connected to your computer Next step is to install the USB Blaster driver if not already done T...

Page 42: ... Hardware Wizard The desired driver is not available on the Windows Update Web site therefore select No not this time and click Next This leads to the window in Figure 6 3 Figure 6 3 The driver is found in a specific location ...

Page 43: ...he best driver in these locations and click Browse to get to the pop up dialog box in Figure 6 5 Find the desired driver which is at location C altera 10 1 quartus drivers usb blaster Click OK and then upon returning to Figure 6 4 click Next At this point the installation will commence but a dialog box in Figure 6 6 will appear indicating that the driver has not passed the Windows Logo testing Cli...

Page 44: ...44 Figure 6 5 Browse to find the location Figure 6 6 There is no need to test the driver ...

Page 45: ...D design you will write Verilog HDL code for a simple 32 bit counter add a phase locked loop PLL megafunction as the clock source and add a 2 input multiplexer megafunction When the design is running on the board you can press an input switch to multiplex the counter bits that drive the output LEDs 6 6 4 4 A As ss si ig gn n T Th he e D De ev vi ic ce e Begin this tutorial by creating a new Quartu...

Page 46: ...Note File names project names and directories in the Quartus II software cannot contain spaces a What is the working directory for this project Enter a directory in which you will store your Quartus II project files for this design For example E My_design my_first_fpga b What is the name of this project Type my_first_fpga c What is the name of the top level design entity for this project Type my_f...

Page 47: ...ure 6 9 Project information d Click Next e In the next dialog box you will assign a specific FPGA device to the design Select the EP4CE22F17C6 device as it is the FPGA on the DE0 Nano as shown in Figure 6 10 ...

Page 48: ...cify the Device Example f Click Finish 4 When prompted select Yes to create the my_first_fpga project directory You just created your Quartus II FPGA project Your project is now open in Quartus II as shown in Figure 6 11 ...

Page 49: ...gafunctions adding pins and interconnecting all the components and pins First create a top level module In this tutorial you will use schematic entry via a Block Design File bdf Alternatively you could use Verilog HDL or VHDL for the top level module The following steps describe how to create the top level schematic 1 Select File New Block Diagram Schematic File see Figure 6 12 to create a new fil...

Page 50: ... BDF 2 Click OK 3 Select File Save As and enter the following information File name my_first_fpga Save as type Block Diagram Schematic File bdf 4 Click Save The new design file appears in the Block Editor see Figure 6 13 ...

Page 51: ...ank block diagram by choosing File New Verilog HDL File 2 Select Verilog HDL File in the tree and Click OK 3 Save the newly created file by selecting File Save As and entering the following information see Figure 6 14 File name simple_counter v Save as type Verilog HDL File v vlg verilog ...

Page 52: ...u to enter the Verilog HDL code 4 Type the following Verilog HDL code into the blank simple_counter v file as shown in Figure 6 15 It has a single clock input and a 32 bit output port module simple_counter CLOCK_5 counter_out input CLOCK_5 output 31 0 counter_out reg 31 0 counter_out ...

Page 53: ...ing the floppy disk icon 6 Select File Create Update Create Symbol Files for Current File to convert the simple_counter v file to a Symbol File sym You will use this Symbol File to add the HDL code to your schematic The Quartus II software creates a Symbol File and displays a message see Figure 6 16 Figure 6 16 Create Symbol File was Successful 7 Click OK 8 To add the simple_counter v symbol to th...

Page 54: ...its icon Figure 6 17 Adding the Symbol to the BDF 12 Click OK 13 Move the cursor to the BDF grid the symbol image moves with the cursor Click to place the simple_counter symbol onto the BDF You can move the block after placing it by simply clicking and dragging it to where you want it and releasing the mouse button to place it See Figure 6 18 Figure 6 18 Placing the simple_counter symbol ...

Page 55: ...o provides more complex functions called MegaCore functions which you can evaluate for free but require a license file for use in production designs This tutorial design uses a PLL clock source to drive a simple counter A PLL uses the on board oscillator DE0 Nano Board is 50 MHz to create a constant clock frequency as the input to the counter To create the clock source you will add a pre built LPM...

Page 56: ...te select Verilog HDL d Under What name do you want for the output file type pll at the end of the already created directory name e Click Next Figure 6 20 MegaWizard Plug In Manager page 2a Selections 5 In the MegaWizard Plug In Manager page 3 of 14 window make the following selections see Figure 6 21 a Confirm that the currently selected device family option is set to Cyclone IV E b For device sp...

Page 57: ...xt Figure 6 21 MegaWizard Plug In Manager page 3 of 14 Selections 6 Unselect all options on MegaWizard page 4 As you turn them off pins disappear from the PLL block s graphical preview See Figure 6 22 for an example ...

Page 58: ...58 Figure 6 22 MegaWizard Plug In Manager page 4 of 14 Selections 7 Click Next four times to get to page 8 8 Set the Clock division factor to 10 as shown in Figure 6 23 ...

Page 59: ...6 23 MegaWizard Plug In Manager page 8 of 14 Selections 9 Click Next and then click Finish 10 The wizard displays a summary of the files it creates see Figure 6 24 Select the pll bsf option and click Finish again ...

Page 60: ...60 Figure 6 24 Wizard Created Files The Symbol window opens showing the newly created PLL megafunction a s shown in Figure 6 25 ...

Page 61: ...ange them See Figure 6 26 Figure 6 26 Place the PLL Symbol 12 Move the mouse so that the cursor also called the selection tool is over the pll symbol s c0 output pin The orthogonal node tool cross hair icon appears 13 Click and drag a bus line from the c0 output to the simple_counter clock input This action ties the pll output to the simple_counter input see Figure 6 27 ...

Page 62: ...input pin to the schematic 1 Right click in the blank area of the BDF and select Insert Symbol 2 Under Libraries select quartus libraries primitives pin input See Figure 6 28 3 Click OK If you need more room to place symbols you can use the vertical and horizontal scroll bars at the edges of the BDF window to view more drawing space Figure 6 28 Input pin symbol ...

Page 63: ...Change the pin name by double clicking pin_name and typing CLOCK_50 see Figure 6 30 This name correlates to the oscillator clock that is connected to the FPGA Adding an Output bus to the Schematic The following steps describe how to add an output bus to the schematic 1 Using the Orthogonal Bus tool draw a bus line connected on one side to the simple_counter output port and leave the other end unco...

Page 64: ...e and select Properties 3 Type counter 31 0 as the bus name see Figure 6 31 The notation X Y is the Quartus II method for specifying the bus width in BDF schematics where X is the most significant bit MSB and Y is the least significant bit LSB 4 Click OK Figure 6 32 shows the BDF ...

Page 65: ... multiplexer to route the simple_counter output to the LED pins on the DE0 Nano development board You will use the MegaWizard Plug In Manager to add the multiplexer lpm_mux The design multiplexes two portions of the counter bus to four LEDs on the DE0 Nano board The following steps describe how to add a multiplexer to the schematic ...

Page 66: ..._MUX 5 Select the Cyclone IV E device family Verilog HDL as the output file type and name the output file counter_bus_mux v as shown in Figure 6 33 6 Click Next Figure 6 33 Selecting lpm_mux 7 Under How many data inputs do you want select 2 inputs default 8 Under How wide should the data input and the result output buses be select 4 as shown in Figure 6 34 ...

Page 67: ...67 Figure 6 34 lpm_mux settings 9 Click Next 10 Click Next 11 Select the counter_bus_mux bsf option 12 Click Finish The Symbol window appears see Figure 6 35 for an example ...

Page 68: ...68 Figure 6 35 lpm_mux Symbol 13 Click OK 14 Place the counter_bus_mux symbol below the existing symbols on the BDF as shown in Figure 6 36 Figure 6 36 Place the lpm_mux symbol ...

Page 69: ...data1x input Because the input busses to counter_bus_mux have the same names as the output bus from simple_counter counter x y the Quartus II software knows to connect these busses e Click OK f Right click the bus line connected to data0x 3 0 and select Properties g Name the bus counter 24 21 which selects only those counter output bits to connect to the four bits of the data1x input h Click OK Fi...

Page 70: ...e 6 39 Rename the output pin 21 Attach an input pin to the multiplexer select line using an input pin a Right click in the blank area of the BDF and select Insert Symbol b Under Libraries double click quartus libraries primitives pin input c Click OK 22 Place this input pin below counter_bus_mux 23 Connect the input pin to the counter_bus_mux sel pin 24 Rename the input pin as KEY 0 see Figure 6 4...

Page 71: ...n t th he e P Pi in ns s In this section you will make pin assignments Before making pin assignments perform the following steps 1 Select Processing Start Start Analysis Elaboration in preparation for assigning pin locations 2 Click OK in the message window that appears after analysis and elaboration completes To make pin assignments to the KEY 0 and CLOCK_50 input pins and to the LED 3 0 output p...

Page 72: ...uble click in the Location column for any of the six pins to open a drop down list and type the location shown in the table Alternatively you can select the pin from a drop down list For example if you type F1 and press the Enter key the Quartus II software fills in the full PIN_F1 location name for you The software also keeps track of corresponding FPGA data such as the I O bank and VREF Group Ea...

Page 73: ...ints File sdc that the Quartus II TimeQuest Timing Analyzer uses during design compilation For more complex designs you will need to consider the timing requirements more carefully To create an SDC perform the following steps 1 Open the TimeQuest Timing Analyzer by choosing Tools TimeQuest Timing Analyzer 2 Select File New SDC file The SDC editor opens 3 Type the following code into the editor cre...

Page 74: ... that can be downloaded into the FPGA The most important output of compilation is an SRAM Object File sof which you use to program the device Also the software generates report files that provide information about your circuit as it compiles Now that you have created a complete Quartus II project and entered all assignments you can compile the design In the Processing menu select Start Compilation...

Page 75: ...I Messages window displays many messages during compilation It should not display any critical warnings it may display a few warnings that indicate that the device timing information is preliminary or that some parameters on the I O pins used for the LEDs were not set The software provides the compilation results in the Compilation Report tab as shown in Figure 6 45 ...

Page 76: ...on the board Set up your hardware for programming using the following steps First connect the USB cable which was included in your development kit between the DE0 Nano and the host computer Refer to the getting started user guide for detailed instructions on how to connect the cables Refer to the getting started user guide for detailed instructions on how to connect the cables Program the FPGA usi...

Page 77: ...77 Figure 6 46 Programmer Window 2 Click Hardware Setup 3 If it is not already turned on turn on the USB Blaster USB 0 option under currently selected hardware as shown in Figure 6 47 ...

Page 78: ...ardware Setting 4 Click Close 5 If the file name in the Programmer does not show my_first_fpga sof click Add File 6 Select the my_first_fpga sof file from the project directory see Figure 6 48 7 Click the Start button ...

Page 79: ...tioning appropriately Verify the design by performing the following steps 1 Observe that the four development board LEDs appear to be advancing slowly in a binary count pattern which is driven by the simple_counter bits 26 23 The LEDs are active low therefore when counting begins all LEDs are turned on the 0000 state 2 Press and hold KEY 0 on the development board and observe that the LEDs advance...

Page 80: ...80 Figure 6 49 Device and Options Select unused pins Reserve all unused pins select the As input tri stated option See Figure 6 50 ...

Page 81: ...ns Click twice OK 4 In the Processing menu choose Start Compilation After the compile select Tools Programmer Select the my_first_fpga sof file from the project directory Click Start At this time you could find the other LEDs are off ...

Page 82: ...equires the Quartus II and Nios II EDS software to be installed The tutorial was written for version 10 1 of those software packages If you are using a different version there may be some difference in the flow Also this tutorial requires the DE0 Nano board 7 7 2 2 C Cr re ea at ti io on n o of f H Ha ar rd dw wa ar re e D De es si ig gn n This section describes the flow of how to create a hardwar...

Page 83: ...Create a New Project Figure 7 2 New Project Wizard 2 Select a working directory for this project type project name and top level entity name as shown in Figure 7 3 Then click Next you will see a window as shown in Figure 7 4 ...

Page 84: ... Wizard Add Files page 2 of 5 3 Click Next to skip in Add Files window In the Family Device Settings window we will choose device family and device settings appropriate for the DE0 Nano board You should choose settings the same as shown in Figure 7 5 Then click Next to get to the window as shown in Figure 7 6 ...

Page 85: ... Wizard Family Device Settings page 3 of 5 4 Click Next and will see a window as shown in Figure 7 7 Figure 7 7 is a summary about the new project Click Finish to complete the New Project Wizard Figure 7 8 show the new project ...

Page 86: ...86 Figure 7 6 New Project Wizard EDA Tool Settings page 4 of 5 Figure 7 7 New Project Wizard Summary page 5 of 5 ...

Page 87: ...87 Figure 7 8 A New Complete Project 5 Select Tools SOPC Builder to open SOPC Builder the Altera system generation tool as shown in Figure 7 9 Figure 7 9 SOPC Builder Menu ...

Page 88: ...88 Figure 7 10 Create New SOPC System 0 6 Rename System Name as shown in Figure 7 10 and Figure 7 11 Click OK and your will see a window as shown in Figure 7 12 Figure 7 11 Create New System 1 ...

Page 89: ...clk_0 to clk_50 Press Enter to complete the update as shown in Figure 7 13 Figure 7 13 Rename Clock Name 8 In the left hand side Component Library tree select Library Processors Nios II Processor and click the Add button to open the Nios II component wizard as shown in Figure 7 14 and Figure 7 15 ...

Page 90: ...90 Figure 7 14 Add NIOS II Processor ...

Page 91: ...91 Figure 7 15 Nios II Processor 9 Click Finish to return to main window as shown in Figure 7 16 ...

Page 92: ...92 Figure 7 16 Add Nios II CPU completely 10 Select the cpu_0 component and right click then select rename after this you can update cpu_0 to cpu as shown in Figure 7 17 and Figure 7 18 ...

Page 93: ...93 Figure 7 17 Rename the CPU 1 Figure 7 18 Rename the CPU 2 ...

Page 94: ...94 11 Add a second component by selecting Library Interface Protocols Serial JTAG UART and clicking the Add button as shown in Figure 7 19 and Figure 7 20 Figure 7 19 Add the JTAG UART component ...

Page 95: ...95 Figure 7 20 JTAG UART s add wizard 12 We are going to use the default settings for this component so click Finish to close the wizard and return to the window as shown in Figure 7 21 ...

Page 96: ...96 Figure 7 21 JTAG UART 13 Select the jtag_uart_0 component and rename it to jtag_uart as shown in Figure 7 22 ...

Page 97: ...97 Figure 7 22 Rename JTAG UART 15 Add the Library Memories and Memory Controllers On Chip On Chip Memory RAM or ROM component to system as shown in Figure 7 23 and Figure 7 24 ...

Page 98: ...98 Figure 7 23 Add On Chip Memory ...

Page 99: ...99 Figure 7 24 On Chip Memory Box 16 Modify Total memory size setting to 26000 as shown in Figure 7 25 Click Finish to return to the window as in Figure 7 26 ...

Page 100: ...100 Figure 7 25 Update Total memory size ...

Page 101: ...p_memory2 as shown in Figure 7 27 Figure 7 27 Rename On Chip memory 18 Right click on the cpu component table and select Edit from the list Update the Reset Vector and Exception Vector as shown in Figure 7 28 Then click Finish to return to the window as shown Figure 7 29 ...

Page 102: ...102 Figure 7 28 Update CPU settings ...

Page 103: ...103 Figure 7 29 Updated CPU settings 19 Add the Library Peripherals Microcontroller Peripherals PIO Parallel I O component to the system as shown in Figure 7 30 and Figure 7 31 ...

Page 104: ...104 Figure 7 30 Add PIO ...

Page 105: ...105 Figure 7 31 Add PIO 20 Click Finish to use the default settings for this component This closes the PIO wizard and returns to the window shown in Figure 7 32 ...

Page 106: ...106 Figure 7 32 PIO 21 Rename pio_0 to pio_led as shown in Figure 7 33 Figure 7 33 Rename PIO ...

Page 107: ...ase Addresses as shown in Figure 7 34 Then select File Refresh System After that you will find that there is no error in the message window as shown in Figure 7 35 Figure 7 34 Auto Assign Base Addresses Figure 7 35 No errors or warnings ...

Page 108: ... which bring up the window in Figure 7 37 Input the name DE0_NANO_SOPC and click the save button The compilation will automatically start If there are no errors in the generation the window will show a message of success as shown in Figure 7 38 Figure 7 36 Generate SOPC Figure 7 37 Generate SOPC ...

Page 109: ...109 Figure 7 38 SOPC Builder generation successful 24 Click Exit to exit the SOPC Builder and return to the window as shown in Figure 7 39 Figure 7 39 Return to Quartus II after exiting SOPC Builder ...

Page 110: ...110 25 Create a new Verilog HDL file by selecting File New Verilog HDL File and click OK as shown in Figure 7 40 and Figure 7 41 Figure 7 40 New Verilog file Figure 7 41 New Verilog File ...

Page 111: ...ile Figure 7 42 A blank verilog file 34 Type the following Verilog into the blank file as shown in Figure 7 43 The module DE0_NANO_SOPC is the system created by SOPC Builder and its Verilog can be found in the DE0_NANO_SOPC v file as shown in ...

Page 112: ...112 Figure 7 44 and Figure 7 45 module myfirst_niosii CLOCK_50 LED input CLOCK_50 output 7 0 LED DE0_NANO_SOPC DE0_NANO_SOPC_inst clk_50 CLOCK_50 out_port_from_the_pio_led LED reset_n 1 b1 endmodule ...

Page 113: ...113 Figure 7 43 Input verilog Text Figure 7 44 Open DE0_NANO_SOPC v ...

Page 114: ...114 Figure 7 45 DE0_NANO_SOPC module 35 Save the newly created Verilog file as myfirst_niosii v as shown in Figure 7 46 Figure 7 46 Save the Verilog file ...

Page 115: ...115 36 Compile the project by selecting Processing Start Compilation as shown in Figure 7 47 Figure 7 48 shows the compilation process Figure 7 47 Start Compilation Figure 7 48 Execute Compile ...

Page 116: ... as shown in Figure 7 49 Figure 7 49 Compile project completely 38 Now we will assign the inputs and outputs of the circuit to specific pins Select Assignments Pin Planner from the menubar as shown in Figure 7 50 The pin planner is shown in Figure 7 51 Figure 7 50 Pins menu ...

Page 117: ...iguration file to the board Download the FPGA configuration file i e the SRAM Object File sof that contains the NIOS II based system to the board by performing the following steps 1 Connect the board to the host computer via the USB download cable 2 Start the NIOS II IDE 3 After the welcome page appears click Workbench 4 Select Tools Quartus II Programmer 5 Click Auto Detect The device on your dev...

Page 118: ...ears 12 Select USB Blaster from the currently selected hardware drop down list box as shown in Figure 7 53 Note If the appropriate download cable does not appear in the list you must first install drivers for the cable Refer to Quartus II Help for information on how to install the driver Figure 7 53 Hardware Setup Window 13 Click Close 14 Make sure the Program Configure option for the programming ...

Page 119: ... II IDE integrates a text editor debugger the Nios II flash programmer the Quartus II Programmer and the Nios II C to Hardware C2H compiler GUI The included example software application templates make it easy for new software programmers to get started quickly In this section you will use the Nios II IDE to compile a simple C language example software program to run on the Nios II system on your d...

Page 120: ...ose the Quartus II Programmer or leave it open in the background if you want to reload the processor system onto your development board quickly 2 Select File New NIOS II C C Application to open the New Project Wizard 3 In the New Project wizard make sure the following things a Select the Hello World project template b Give the project a name hello_world_0 is default name c Select the target hardwa...

Page 121: ...121 Figure 7 55 Nios II IDE New Project Wizard 5 Click Finish The NIOS II IDE creates the hello_world_0 project and returns to the NIOS II C C project perspective as shown in Figure 7 56 ...

Page 122: ... When you build the system library for the first time the NIOS II IDE automatically generates files useful for software development including Installed IP device drivers including SOPC component device drivers for the NIOS II hardware system Newlib C library a richly featured C library for the NIOS II processor NIOS II software packages which includes NIOS II hardware abstraction layer Nichestack ...

Page 123: ...ojects tab and select Build Project The Build Project dialog box appears and the IDE begins compiling the project When compilation completes a message Build complete will appear in the Console tab as shown in Figure 7 57 Figure 7 57 Nios II IDE hello_world_0 Build Completed Note If there appears in the console tab an error region onchip_memory2 is full hello_world_0 elf section text Region needs t...

Page 124: ...tware program based on NIOS II And you can perform additional operations such as configuring the system properties editing and re building the application and debugging the source code 7 7 6 6 E Ed di it t a an nd d R Re e R Ru un n t th he e P Pr ro og gr ra am m You can modify the hello_world c program file in the IDE build it and re run the program to observe your changes as it executes on the ...

Page 125: ...delay 2000000 delay count return 0 2 Save the project 3 Recompile the project by right clicking hello_world_0 in the NIOS II C C Projects tab and choosing Run Run As Nios II Hardware Note You do not need to build the project manually the Nios II IDE automatically re builds the program before downloading it to the FPGA 4 Orient your development board so that you can observe LEDs blinking ...

Page 126: ... The Nios II processor controls the PIO ports and thereby the LEDs by reading and writing to the register map For the PIO there are four registers data direction interruptmask and edgecapture To turn the LED on and off the application writes to the PIO s data register The PIO core has an associated software file altera_avalon_pio_regs h This file defines the core s register map providing symbolic ...

Page 127: ...tions 7 7 8 8 D De eb bu ug gg gi in ng g t th he e A Ap pp pl li ic ca at ti io on n Before you can debug a project in the NIOS II IDE you need to create a debug configuration that specifies how to run the software To set up a debug configuration perform the following steps 1 In the hello_world c double click the front of the line where you would like to set breakpoint as shown in Figure 7 60 Fig...

Page 128: ...The Properties for hello_world_0_syslib dialog box opens 2 Click System Library in the tree on the left side The System Library page contains settings related to how the program interacts with the underlying hardware The settings have names that correspond to the targeted NIOS II hardware 3 In the Linker Script box observe which memory has been assigned for Program memory text Read only data memor...

Page 129: ...ose the Properties for hello_world_0_syslib dialog box and return to the IDE workbench Note If you make changes to the system properties you must rebuild your project To rebuild right click the hello_world_0 project in the Nios II C C Projects tab and select Build Project ...

Page 130: ... L LE ED Ds s This demonstration shows how to use the FPGA to control the luminance of the LEDs by means of pulse width modulation PWM scheme The LEDs are divided into two groups while one group dims the other group brightens vice versa Users can change the PWM wave s duty ratio and frequency to control the LED luminance and repetition rate Figure 8 1 Shows a diagram of PWM signals to drive LED ...

Page 131: ...t tc ch h F Fi il le e Demo Batch File Folder DE0_NANO_Default demo_batch The demo batch file includes the following files FPGA Configure File DE0_NANO sof D De em mo on ns st tr ra at ti io on n S Se et tu up p Make sure Quartus II and Nios II are installed on your PC Connect USB cable to the DE0 Nano board and install the USB Blaster driver if necessary Execute the demo batch file DE0_NANO bat u...

Page 132: ... measurements are indicated on the 8 LEDs Since there are only 8 LEDs only bit 4 through bit 11 from the ADC are represented on the LEDs Design Concept This section describes the design concepts for this demo Figure 8 3 shows the block diagram Figure 8 3 ADC Reading Block Diagram The ADC Controller reads the voltage from the A D converter through a serial interface and displays its measurement on ...

Page 133: ...alog_In0 0001 Analog_In1 0010 Analog_In2 0011 Analog_In3 0100 Analog_In4 0101 Analog_In5 0110 Analog_In6 0111 Analog_In7 Figure 8 4 depicts the pin arrangement of the 2X13 header Connect the trimmer to the ADC channel which is selected by the DIP Switches Analog_In0 Analog_In7 ...

Page 134: ...System Requirements The following items are required for the ADC Reading demonstration DE0 Nano board x1 Trimmer Potentiometer x1 Wire Strip x3 Hardware Setup Figure 8 5 shows the hardware setup for the ADC Reading demonstration ...

Page 135: ...onfigure File DE0_NANO sof D De em mo on ns st tr ra at ti io on n S Se et tu up p Make sure Quartus II is installed on your PC Connect the trimmer to corresponding ADC channel to read from as well as the 3 3V and GND signals Adjust the DIP switch according to the ADC channel connected Connect USB cable to the DE0 Nano board and install the USB Blaster driver if necessary Execute the demo batch fi...

Page 136: ...bes the SOPC System Block Diagram of this demo as shown in Figure 8 6 Figure 8 6 SOPC Block Diagram A 50 MHz Clock is required for the SOPC System A NIOS II processor is included in the system for flow control The PLL is used to generate clocks including 100 MHz 10 MHz and 2MHz The NIOS II Processor and SDRAM are running at 100 MHZ The SDRAM is used to store the NIOS II Program The ADC SPI Control...

Page 137: ...bled in the PIO Controller Users can enable it with the parameter setting as shown in below Figure 8 7 Figure 8 7 PIO Controller Accelerometer Control The accelerometer controller is a custom SOPC component developed by Terasic The source code is available under the folder DE0_NANO_SOPC_DEMO ip TARASIC_SPI_3WIRE In this demo the accelerometer is controlled through a 3 wire SPI Before reading any d...

Page 138: ...cant byte where x represent X Y or Z Figure 8 9 Register 0x30 The SPI timing scheme follows clock polarity CPOL 1 and clock phase CPHA 1 CPOL 1 means the clock is high in idle CPHA 1 means data is captured on clock s rising edge and data is propagated on a falling edge The timing diagram of 3 wire SPI is shown below Figure 8 10 Figure 8 10 3 wire SPI Timing Diagram ADC Control The Analog to Digita...

Page 139: ...iver by a BIDIRECTION PIO Controller The I2C C code is located in DE0_NANO_SOPC_DEMO software DE0_NANO terasic_lib I2C c EPCS Control EPCS64 is accessed through the EPCS interface In Quartus 10 0 or later the EPCS pin assignment is required and should be connected the pins to EPCS Controller as shown below Figure 8 12 Figure 8 12 EPCS interface connection For the EPCS access functions users can re...

Page 140: ...t ti io on n S Se et tu up p Make sure Quartus II and Nios II are installed on your PC Connect a USB cable to the DE0 Nano board and install USB Blaster driver if necessary Execute the demo batch file test bat under the batch file folder DE0_NANO_SOPC_DEMO demo_batch This will load the demo into the FPGA After executing the batch file a selection menu appears as follows Input 0 to start the accele...

Page 141: ...ano board Upon exiting the demo the selection menu will be displayed Input 2 to start EEPROM Content Dump demo The demo displays the values in the first 16 bytes of the EEPROM The demo automatically exists and returns to the selection menu Input 3 to start EPCS demo The demo displays the memory size of EPCS The demo automatically exists and returns to the selection menu ...

Page 142: ...f gravity in tilt sensing applications As the board is tilted from left to right and right to left the digital accelerometer detects the tilting movement and displays it on the LEDs Figure 8 13 DE0 Nano on level surface Design Concept This section describes the design concepts for this demo Figure 8 14 shows the block diagram Figure 8 14 G Sensor block diagram ...

Page 143: ...I is installed on your PC Connect USB cable to the DE0 Nano board and install the USB Blaster driver if necessary Execute the demo batch file test bat under the batch file folder DE0_NANO_GSensor demo_batch This will load the demo into the FPGA Tilt the DE0 Nano board from side to side and observe the result on the LEDs 8 8 6 6 S SD DR RA AM M T Te es st t b by y N Ni io os s I II I Many applicati...

Page 144: ...he SDRAM Then it calls Nios II system function alt_dcache_flush_all to make sure all data has been written to SDRAM Finally it reads data from SDRAM for data verification The program will show progress in JTAG Terminal when writing reading data to from the SDRAM When verification process is completed the result is displayed in the JTAG Terminal Design Tools Quartus II 13 0 SP1 Nios II Eclipse 13 0...

Page 145: ...t sof Nios II Program DE0_NANO_SDRAM_Nios_Test elf Demonstration Setup Make sure Quartus II and Nios II are installed on your PC Connect a USB cable to the DE0 Nano board and install USB Blaster driver if necessary Execute the demo batch file DE0_NANO_SDRAM_Nios_Test bat under the batch file folder DE0_NANO_SDRAM_Nios_Test demo_batch After Nios II program is downloaded and executed successfully a ...

Page 146: ...146 Figure 8 16 Display Progress and Result Information for the SDRAM Demonstration ...

Page 147: ...of the circuit they wish to put in the serial configuration device Next users need to convert the SOF to a JIC file To convert a SOF to a JIC file in Quartus II software follow these steps Convert SOF to JIC 1 Select File Convert Programming Files 2 In the Convert Programming Files dialog box set the Programming file type field to JTAG Indirect Configuration File jic 3 In the Configuration device ...

Page 148: ...148 9 Highlight the Flash Loader and click Add Device as shown in Figure 9 2 10 Click OK The Select Devices page displays Figure 9 1 Convert Programming Files Dialog Box ...

Page 149: ...rgeted FPGA Cyclone IV E EP4CE22 as shown in Figure 9 3 12 Click OK The Convert Programming Files page displays should look like Figure 9 4 13 Select the sof file and Click the Properties Select Compression click OK as shown in Figure 9 5 14 Click Generate ...

Page 150: ...150 Figure 9 3 Select Devices Page ...

Page 151: ...151 Figure 9 4 Convert Programming Files Page ...

Page 152: ...le that you just created add the file to the Quartus II Programmer window and follow the steps 1 When the SOF to JIC file conversion is complete add the JIC file to the Quartus II Programmer window i Select Tools Programmer The Chain1 cdf window displays ii Click Add File From the Select Programming File page browse to the JIC file iii Click Open ...

Page 153: ...Click Start to program serial configuration device Erase the Serial Configuration Device To erase the existed file in the serial configuration device follow the steps listed below 1 Select Tools Programmer The Chain1 cdf window displays 2 Click Add File From the Select Programming File page browse to a JIC file 3 Click Open 4 Erase the serial configuration device by checking the corresponding Eras...

Page 154: ...154 default SFL image will be load See Figure 9 7 Figure 9 7 Erasing setting in Quartus II programmer window 5 Click Start to erase the serial configuration device ...

Page 155: ...as shown in Figure 9 8 Figure 9 8 EPCS Message 9 9 3 3 R Re ev vi is si io on n H Hi is st to or ry y Version Change Log V1 0 Initial Version Preliminary V1 3 Add Table 3 1 3 2 and 3 3 V1 4 Modified Digital Accelerometer Description on page 31 V1 5 Modified ADC description on page 32 V1 6 Corrected Digital Accelerometer Schematic on page 23 V1 7 Modified Altera EPCS16 to be Spansion EPCS64 V1 8 Ad...

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