Terasic De0-Nano, User Manual

Page: 15 / 155

15
Table 3-3 Pin Assignments for DIP Switches
Signal Name FPGA Pin No. Description I/O Standard
DIP Switch[0] PIN_M1 DIP Switch[0] 3.3V
DIP Switch[1] PIN_T8 DIP Switch[1] 3.3V
DIP Switch[2] PIN_B9 DIP Switch[2] 3.3V
DIP Switch[3] PIN_M15 DIP Switch[3] 3.3V
3
3
.
.
3
3
S
S
D
D
R
R
A
A
M
M
M
M
e
e
m
m
o
o
r
r
y
y
The board features a Synchronous Dynamic Random Access Memory (SDRAM) device providing
32MB with a 16-bit data lines connected to the FPGA. The chip uses 3.3V LVCMOS signaling
standard. All signals are registered on the positive edge of the clock signal, DRAM_CLK.
Connections between the FPGA and SDRAM chips are shown in
Figure 3-6 .
Figure 3-6 Connections between FPGA and SDRAM
Table 3-4 SDRAM Pin Assignments
Signal Name FPGA Pin No. Description I/O Standard
DRAM_ADDR[0] PIN_P2 SDRAM Address[0] 3.3V
DRAM_ADDR[1] PIN_N5 SDRAM Address[1] 3.3V
DRAM_ADDR[2] PIN_N6 SDRAM Address[2] 3.3V
DRAM_ADDR[3] PIN_M8 SDRAM Address[3] 3.3V
DRAM_ADDR[4] PIN_P8 SDRAM Address[4] 3.3V
DRAM_ADDR[5] PIN_T7 SDRAM Address[5] 3.3V
DRAM_ADDR[6] PIN_N8 SDRAM Address[6] 3.3V
DRAM_ADDR[7] PIN_T6 SDRAM Address[7] 3.3V
DRAM_ADDR[8] PIN_R1 SDRAM Address[8] 3.3V
DRAM_ADDR[9] PIN_P1 SDRAM Address[9] 3.3V
DRAM_ADDR[10] PIN_N2 SDRAM Address[10] 3.3V
DRAM_ADDR[11] PIN_N1 SDRAM Address[11] 3.3V