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Controller Area Network
LH75400/01/10/11 (Preliminary) User’s Guide
22-32
6/17/03
NOTES
1. Software Reset (MOD.0) or Bus Off.
2. If the Reset Mode was entered due to a Bus Off condition, the Error Warning Interrupt will be set (if enabled).
3. If the Reset Mode was entered due to a Bus Off condition, the Receive Error Counter is cleared and the
Transmit Error Counter is initialized to 127 to count-down the CAN-defined Bus Off recovery time
consisting of 128 occurrences of 11 consecutive recessive bits.
22.3.4 CAN Acceptance Filtering
The CAN Controller filters the incoming data stream, discarding any message that does
not have the required bit pattern in its identifier.
The bit pattern against which the message identifier is recorded in the Acceptance Code
Registers (ACR0 through ACR3), masked by the values recorded in the Acceptance Mask
Registers (AMR0 through AMR3).
• A value of 0 in AMR0 through AMR3 identifies the bits at the corresponding positions in
ACR0 through ACR3, which must be matched in the message identifier.
• A value 1 identifies the corresponding bits as ‘don’t care’.
The bit patterns recorded in the ACR0 - ACR3 Registers can be used as either a single 4-byte
filter or as two shorter filters. The selection is made through the AFM bit (bit [3]) of the Mode
Register (see Section 22.3.2.1).
• If AFM = 1, a single filter is applied.
• if AFM = 0, two filters are applied. When two filters are used, the incoming message is
accepted if its identifier matches either filter.
Transmit Buffer
TXB
Transmit Buffer
x
x
Receive Buffer
RXB
Receive Buffer
x
x
Acceptance Code Registers 0-3
ACR0 - ACR3 Acceptance Code Registers 0-3
00h
x
Acceptance Mask Registers 0-3
—
AMR0 - AMR3 Acceptance Mask Registers 0-3
00h
x
Receive Message Count
—
RMC
Receive Message Count
0
0
Receive Buffer Start Address
—
RBSA
Receive Buffer Start Address
00h
x
Receive FIFO
—
—
Receive FIFO
x
x
Table 22-38. Effect of Reset on CAN Controller Registers (Cont’d)
REGISTER
BIT
SYMBOL
NAME
RESET VALUE
NOTES
SYSTEM
SOFTWARE