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LH75400/01/10/11 (Preliminary) User’s Guide

Color Liquid Crystal Display Controller

7/15/03

 13-11

13.3.2 CLCDC Register Definitions

13.3.2.1 Horizontal Timing Panel Control Register

The Timing0 Register controls: 

• Horizontal Synchronization Pulse Width (HSW)

• Horizontal Front Porch (HFP) period 

• Horizontal Back Porch (HBP) period

• Pixels-Per-Line (PPL) 

 

Table 13-10. Timing0 Register

BIT

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

FIELD

HBP

HFP

RESET

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

BIT

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FIELD

HSW

PPL

///

RESET

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

R

R

ADDR

0xFF 0x00

Table 13-11. Timing0 Register Definitions

BIT

NAME

DESCRIPTION

31:24

HBP

Horizontal Back Porch

Specifies the number of LCDDCLK periods between 

the falling edge of LCDLP and the start of active data; that is, the number of pixel 
clock periods inserted at the beginning of each line or row of pixels. Program 
with value minus 1. After the line clock for the previous line has been de-assert-
ed, the value in HBP counts the number of pixel clocks to wait before starting the 
next display line. HBP can generate a delay of 1 to 256 pixel clock cycles.

23:16

HFP

Horizontal Front Porch

Specifies the number of LCDDCLK periods between 

the end of active data and the rising edge of LCDLP; that is, the number of pixel 
clock intervals at the end of each line or row of pixels before the LCD line clock 
is pulsed. Program with value minus 1. Once a complete line of pixels is trans-
mitted to the LCD driver, the value in HFP counts the number of pixel clocks to 
wait before asserting the line clock. HFP can generate a period of 1 to 256 pixel 
clock cycles.

15:8

HSW

Horizontal Synchronization Pulse Width

Specifies the width of the LCDLP 

signal in LCDDCLK periods; that is, the pulse width of the line clock in Passive 
Mode or the horizontal synchronization pulse in Active Mode. Program with 
value minus 1.

7:2

PPL

Pixels-Per-Line

Specifies the number of pixels, between 16 and 1,024, in 

each line or row of the screen. PPL counts the number of pixel clocks that occur 
before the HFP is applied (program the value required divided by 16, minus 1).

1:0

///

Reserved

Writing to these bits has no effect. Reading returns 0.

Summary of Contents for Blue Treak LH75400

Page 1: ...LH75400 01 10 11 System on Chip Preliminary User s Guide 7 15 03 ...

Page 2: ...IFICALLY EXCLUDED In no event will Sharp be liable or in any way responsible for any incidental or consequential economic or property damage BlueStreak is a trademark pending of SHARP Microelectronics of the Americas ARM7TDMI S is a trademark of Advanced RISC Machines United Kingdom Motorola SPI is a trademark of Motorola Inc National Semiconductor Microwire is a trademark of National Semiconducto...

Page 3: ... 1 Linear Regulator Power 1 5 1 5 1 1 PLL Power 1 5 1 5 1 2 PCB Mounted Analog Power Supply Filter for PLL Usage 1 5 1 5 2 Real World Component Selection 1 6 1 6 Crystal Oscillator Usage 1 7 1 7 Clocking Strategy 1 7 1 8 Reset Strategy 1 8 Chapter 2 LH75401 SoC 2 1 LH75401 Features 2 1 2 2 LH75401 Block Diagram 2 2 2 3 LH75401 Applications 2 3 2 4 LH75401 Pin Diagram 2 4 2 5 LH75401 Numerical Pin ...

Page 4: ... Burst Mode Read Process 7 4 7 2 4 External Memory Bus Cycle 7 8 7 2 5 External Bus Read Write Operations 7 9 7 2 6 SMC Memory Connection Diagram 7 11 7 3 SMC Programmer s Model 7 12 7 3 1 SMC Register Summary 7 12 7 3 2 SMC Register Definitions 7 13 7 3 2 1 Configuration Register for Memory Bank 0 7 13 7 3 2 2 Configuration Register for Memory Bank 1 7 15 7 3 2 3 Configuration Register for Memory...

Page 5: ... Interrupt Controller 10 1 Theory of Operation 10 1 10 1 1 Interrupts 10 1 10 1 2 VIC Interrupt Listing 10 2 10 1 3 Vectored Interrupts 10 3 10 1 4 External Interrupts 10 3 10 1 5 Clearing Interrupts 10 4 10 1 6 Priority 10 4 10 1 7 Sequencing 10 5 10 1 8 External Level Sensitive Interrupts 10 7 10 1 9 Software Guidelines 10 7 10 2 VIC Programmer s Model 10 7 10 2 1 VIC Register Summary 10 8 10 2 ...

Page 6: ...ntroller 12 1 DMA Controller Features 12 1 12 2 DMA Theory Of Operation 12 2 12 2 1 Interrupt Error and Status Registers 12 4 12 2 2 DMA Controller Timing Diagrams 12 4 12 3 DMA Programmer s Model 12 7 12 3 1 DMA Controller Register Summary 12 7 12 3 2 DMA Controller Register Definitions 12 8 12 3 2 1 Source Base Registers 12 8 12 3 2 2 Destination Base Register 12 8 12 3 2 3 Maximum Count Registe...

Page 7: ... 13 4 1 2 HR TFT Mode 13 24 13 4 2 HRTFTC Theory of Operation 13 25 13 4 3 HRTFTC Programmer s Model 13 25 13 4 4 HRTFTC Register Summary 13 25 13 4 5 HRTFTC Register Definitions 13 26 13 4 5 1 Setup Register 13 26 13 4 5 2 Control Register 13 27 13 4 5 3 Timing1 Register 13 28 13 4 5 4 Timing2 Register 13 29 13 5 Timing Waveforms 13 30 13 5 1 STN Horizontal Timing 13 30 13 5 2 STN Vertical Timing...

Page 8: ...nal Sampling 15 7 15 1 4 PWM Mode 15 7 15 2 Timer Programmer s Model 15 9 15 2 1 Timer Register Summary 15 9 15 2 2 Timer Register Definitions 15 10 15 2 2 1 Timer 0 Control Register 15 10 15 2 2 2 Timer 0 Compare Capture Control Register 15 11 15 2 2 3 Timer 0 Interrupt Control Register 15 13 15 2 2 4 Timer 0 Status Register 15 14 15 2 2 5 Timer 0 Counter Register 15 15 15 2 2 6 Timer 0 Compare R...

Page 9: ... 4 17 3 2 2 Data Register 1 17 5 17 3 2 3 Match Register 0 17 6 17 3 2 4 Match Register 1 17 6 17 3 2 5 Interrupt Status Clear 17 7 17 3 2 6 Read Write Load Register 0 17 8 17 3 2 7 Read Write Load Register 1 17 9 17 3 2 8 Control Register 17 10 17 3 3 RTC Interrupts 17 10 Chapter 18 Synchronous Serial Port 18 1 SSP Features 18 1 18 2 SSP Theory Of Operation 18 3 18 3 SSP Timing Waveforms 18 4 18 ...

Page 10: ...e Control Register 19 11 19 3 1 5 Integer Baud Rate Divisor Register 19 12 19 3 1 6 Fractional Baud Rate Divisor Register 19 13 19 3 1 7 Calculating the Divisor Value 19 14 19 3 1 8 Typical Bit Rates and Their Corresponding Divisor 19 14 19 3 1 9 Line Control Register 19 15 19 3 1 10 UART Control Register 19 17 19 3 1 11 Interrupt FIFO Level Select Register 19 18 19 3 1 12 Interrupt Mask Set Clear...

Page 11: ...27 20 3 2 17 Receive Machine Status Register 20 28 20 3 2 18 Transmit Command Register 20 29 20 3 2 19 Internal Command Register 20 30 20 3 2 20 General Status Register 20 31 20 3 2 21 FIFO Mode Register 20 32 20 3 2 22 Transmit Machine Mode Register 20 33 20 3 2 23 Internal Mode Register 20 34 20 3 2 24 Address Control Character Register 1 20 35 20 3 2 25 Receive Interrupt Enable Register 20 36 2...

Page 12: ...ntroller Area Network 22 1 CAN 2 0B Features 22 2 22 2 CAN Theory of Operation 22 2 22 2 1 Protocols 22 3 22 2 2 Frame Types 22 3 22 2 2 1 Message Frame 22 3 22 2 2 2 Remote Frame 22 4 22 2 2 3 Bit Errors 22 4 22 2 2 4 Message Errors 22 4 22 2 2 5 Acknowledgement Errors 22 4 22 2 3 Transmitted and Received Data 22 4 22 2 4 Time Delays 22 5 22 2 5 Bus Timing 22 5 22 2 6 Bus Arbitration 22 5 22 2 7 ...

Page 13: ...Summary 23 8 23 3 2 ADC Register Definitions 23 9 23 3 2 1 High Word Register 23 9 23 3 2 2 Control Bank Low Word Register 23 11 23 3 2 3 Results Register 23 12 23 3 2 4 Interrupt Masking Enabling Register 23 13 23 3 2 5 Power Configuration Register 23 14 23 3 2 6 General Configuration Register 23 16 23 3 2 7 Sequence Start Mode Issues 23 17 23 3 2 8 General Status Register 23 18 23 3 2 9 Interrup...

Page 14: ...her Circuit Board Layout Practices 25 3 Chapter 26 Register Map 26 1 SMC Registers 26 1 26 2 RCPC Registers 26 2 26 3 VIC Registers 26 3 26 4 IOCON Registers 26 5 26 5 DMA Controller Registers 26 5 26 6 DMA Stream Registers 26 6 26 7 CLCDC Registers 26 7 26 8 HR TFTC Registers 26 7 26 9 LCDC Registers 26 8 26 10 Timer Registers 26 9 26 11 WDT Registers 26 10 26 12 RTC Registers 26 10 26 13 SSP Reg...

Page 15: ...apter 4 LH75400 SoC Figure 4 1 LH75400 Block Diagram 4 2 Figure 4 2 LH75400 System Application Example 4 3 Figure 4 3 LH75400 Pin Diagram 4 4 Chapter 5 LH75410 SoC Figure 5 1 LH75410 Block Diagram 5 2 Figure 5 2 LH75410 System Application Example 5 3 Figure 5 3 LH75410 Pin Diagram 5 4 Chapter 7 Static Memory Controller Figure 7 1 SMC Write Access 7 3 Figure 7 2 SMC Write nCSx De asserted Early 7 5...

Page 16: ... Figure 15 7 Capture Signal Synchronization Timing 15 7 Figure 15 8 PWM Output Signal Timing 15 8 Chapter 16 Watchdog Timer Figure 16 1 Watchdog Timer Block Diagram 16 1 Chapter 17 Real Time Clock Figure 17 1 RTC Block Diagram 17 1 Chapter 18 Synchronous Serial Port Figure 18 1 Synchronous Serial Port Block Diagram 18 2 Figure 18 2 SSP Timing Waveform 18 4 Figure 18 3 Motorola SPI Frame Format Sin...

Page 17: ...o Digital Converter Brownout Detector Figure 23 1 ADC Block Diagram 23 2 Figure 23 2 Bias and Control Network Block Diagram 23 4 Figure 23 3 Simplified N bit SAR Architecture 23 5 Figure 23 4 Example of a 4 bit SAR ADC Operation 23 6 Figure 23 5 Bias and Control Network Block Diagram 23 28 Chapter 25 Recommended Layout Practices Figure 25 1 ESD Filter Circuit Example 25 1 Figure 25 1 VDD_PLL VSSA_...

Page 18: ... 5 5 Table 5 2 LH75410 Signal Descriptions 5 9 Chapter 6 Memory Interface Architecture Table 6 1 Memory Mapping 6 2 Table 6 2 External Memory Section Mapping 6 3 Table 6 3 Primary AHB Peripheral Register Mapping 6 3 Table 6 4 APB Peripheral Register Mapping 6 4 Chapter 7 Static Memory Controller Table 7 1 Address Bus Organization 7 1 Table 7 2 SMC Bus Turnaround Usage 7 8 Table 7 3 8 bit External ...

Page 19: ...tions 9 12 Table 9 17 SysClkPrescaler Register Values 9 12 Table 9 18 APBPeriphClkCtrl0 Register 9 13 Table 9 19 APBPeriphClkCtrl0 Register Definitions 9 13 Table 9 20 APBPeriphClkCtrl1 Register 9 14 Table 9 21 APBPeriphClkCtrl1 Register Definitions 9 14 Table 9 22 AhbClkCtrl Register 9 15 Table 9 23 AhbClkCtrl Register Definitions 9 15 Table 9 24 LCDPrescaler Register 9 16 Table 9 25 LCDPrescaler...

Page 20: ...ter 16 bit Mode 11 3 Table 11 3 EBI_MUX Register 8 bit Mode 11 3 Table 11 4 EBI_MUX Register Definitions 11 4 Table 11 5 PD_MUX Register 11 5 Table 11 6 PD_MUX Register Definitions 11 5 Table 11 7 PE_MUX Register LH75401 and LH75400 11 6 Table 11 8 PE_MUX Register LH75410 and LH75411 11 6 Table 11 9 PE_MUX Register Definitions 11 7 Table 11 10 TIMER_MUX Register 11 8 Table 11 11 TIMER_MUX Register...

Page 21: ...els 13 8 Table 13 6 Supported Color STN LCD Panels 13 8 Table 13 7 Supported Mono STN LCD Panels 13 8 Table 13 8 Color STN Intensities From Gray Scale Modulation 13 9 Table 13 9 CLCDC Register Summary 13 10 Table 13 10 Timing0 Register 13 11 Table 13 11 Timing0 Register Definitions 13 11 Table 13 12 Timing1 Register 13 13 Table 13 13 Timing1 Register Definitions 13 13 Table 13 14 Timing2 Register ...

Page 22: ...mmary 14 7 Table 14 7 Timing0 Register 14 8 Table 14 8 Timing0 Register Definitions 14 8 Table 14 9 Timing1 Register 14 10 Table 14 10 Timing1 Register Definitions 14 10 Table 14 11 Timing2 Register 14 11 Table 14 12 Timing2 Register Definitions 14 11 Table 14 13 UPBASE Register 14 12 Table 14 14 UPBASE Register Definitions 14 12 Table 14 15 LPBASE Register 14 13 Table 14 16 LPBASE Register Defini...

Page 23: ...nitions 15 17 Table 15 18 CTRL Register 15 18 Table 15 19 CTRL Register Definitions 15 18 Table 15 20 INT_CTRL Register 15 20 Table 15 21 INT_CTRL Register Definitions 15 20 Table 15 22 Status Register 15 21 Table 15 23 Status Register Definitions 15 21 Table 15 24 CNT Register 15 22 Table 15 25 CNT Register Definitions 15 22 Table 15 26 CMP n Registers 15 23 Table 15 27 CMP n Register Definitions...

Page 24: ...4 DR1 Register 17 5 Table 17 5 DR1 Register Definitions 17 5 Table 17 6 MR0 Register 17 6 Table 17 7 MR0 Register Definitions 17 6 Table 17 8 MR1 Register 17 6 Table 17 9 MR1 Register Definitions 17 6 Table 17 10 STAT EOI Register Write Operations 17 7 Table 17 11 STAT EOI Register Definitions Write Operations 17 7 Table 17 12 STAT EOI Register Read Operations 17 7 Table 17 13 STAT EOI Register De...

Page 25: ...ns Read Operations 19 9 Table 19 8 FR Register 19 10 Table 19 9 FR Register Definitions 19 10 Table 19 10 Updating Register Contents 19 11 Table 19 11 IBRD Register 19 12 Table 19 12 IBRD Register Definitions 19 12 Table 19 13 FBRD Register 19 13 Table 19 14 FBRD Register Definitions 19 13 Table 19 15 Bit Rates and Their Corresponding Divisors 19 14 Table 19 16 LCTRL_H Register 19 15 Table 19 17 L...

Page 26: ...egister Definitions 20 17 Table 20 23 Character Bit Lengths 20 18 Table 20 21 Parity Modes 20 18 Table 20 22 Stop Bit Lengths 20 18 Table 20 24 MCTRL Register Bank 0 20 19 Table 20 25 MCTRL Register Bank 1 20 19 Table 20 26 MCTRL Register Definitions 20 19 Table 20 27 LSR Register 20 20 Table 20 28 LSR Register Definitions 20 20 Table 20 29 ACTRL0 Register 20 21 Table 20 30 ACTRL0 Register Definit...

Page 27: ...s 20 39 Table 20 67 BBL Register 20 40 Table 20 68 BBL Register Definitions 20 40 Table 20 69 BBH Register 20 41 Table 20 70 BBH Register Definitions 20 41 Table 20 71 BBCF Register 20 42 Table 20 72 BBCF Register Definitions 20 42 Table 20 73 TMIE Register 20 43 Table 20 74 TMIE Register Definitions 20 43 Table 20 75 Interrupt Service Requirements 20 45 Chapter 21 General Purpose Input Output Tab...

Page 28: ... Table 21 37 PJDR Register 21 21 Table 21 38 PJDR Register Definitions 21 21 Table 21 39 PIDDR Register 21 22 Table 21 40 PIDDR Register Definitions 21 22 Chapter 22 Controller Area Network Table 22 1 CAN Register Summary 22 7 Table 22 2 MOD Register 22 8 Table 22 3 MOD Register Definitions 22 8 Table 22 4 CMR Register 22 9 Table 22 5 CMR Register Definitions 22 9 Table 22 6 SR Register 22 10 Tabl...

Page 29: ... 22 42 Extended Frame Format Dual Filters Receive Buffer 22 33 Chapter 23 Analog to Digital Converter Brownout Detector Table 23 1 Summary of ADC Registers 23 8 Table 23 2 HW Register 23 9 Table 23 3 HW Register Definitions 23 9 Table 23 4 In Mux Definition 23 10 Table 23 5 LW Register 23 11 Table 23 6 LW Register Definitions 23 11 Table 23 7 RR Register 23 12 Table 23 8 RR Register Definitions 23...

Page 30: ...ntroller Register Summary 26 5 Table 26 6 DMA Stream Register Summary 26 6 Table 26 7 CLCDC Register Summary 26 7 Table 26 8 HRTFTC Register Summary 26 7 Table 26 9 LCDC Register Summary 26 8 Table 26 10 Timer 0 Register Summary 26 9 Table 26 11 Timer 1 Register Summary 26 9 Table 26 12 Timer 1 Register Summary 26 9 Table 26 13 WDT Register Summary 26 10 Table 26 14 RTC Register Summary 26 10 Tabl...

Page 31: ...Web site at www arm com Supplemental Documentation An abridged version of this User s Guide and containing the Electrical Characteristics is available as a Data Sheet An even more abbreviated version is available as a single page Product Brief Please contact your local SHARP representative for details or visit the SHARP Microelectronics of the Americas Web site at www sharpsma com Terms and Conven...

Page 32: ...SOCs are built using the ARM7TDMI S RISC core as a base Objects within the chip but external to the core processor and its support devices are referred to throughout this Guide as Peripheral Devices All four SoCs include two buses An Advanced High Performance Bus AHB An Advanced Peripheral Bus APB The devices shown on the APB in the block diagrams are an example of peripheral devices in this docum...

Page 33: ...l values are expressed with UPPER CASE letters and prefixed with 0x as in 0x0FBC All numeric values not specifically identified with the above prefixes as either binary or hexadecimal are decimal values Table 1 Register Name BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD F31 F30 F29 F28 F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW ...

Page 34: ...re 1 shows an example of a multiplexer with three inputs and one output the result Block diagrams can include symbols representing registers and the bit fields within them Figure 2 shows that the BITFIELDNAME bit field in the REGISTERNAME register enables or disables the signal named OUTPUT Figure 1 Multiplexer FUNCTION OUTPUT CONTROL SIGNAL or REGISTER BITFIELD LH754xx 83 INPUT INPUT INPUT Figure...

Page 35: ...t field has no name the register is shown with numbers indicating the appropriate bit positions with the least significant bit on the right as in Figure 4 This bit ordering matches that of the register tables shown in Table 1 Figure 3 Register with Multiple Bit Fields Named REGISTERNAME BITFIELDNAME BITFIELDNAME LH754xx 85 OUTPUT INPUT f Figure 4 Register with Bit Field Named REGISTERNAME 15 3 OUT...

Page 36: ...file Quad Flat Pack LQFP package NOTE In this User s Guide the nonspecific term SoC or device refers collectively to all four SoCs Where information pertains to certain SoCs only those devices are clearly identified Table 1 1 Feature Summary FEATURE LH75401 LH75411 LH75400 LH75410 Static Random Access Memory Controller X X X X Static Memory Controller X X X X Direct Memory Access Controller X X X ...

Page 37: ...f the two instruction sets running on a single Thumb aware core makes these devices effective solutions to the code size and performance problems of 16 bit sys tems And since the thumb aware core is simply an extension of the ARM architecture designers can Compile for Thumb code ARM code or a mix of both Retain 32 bit RISC performance 1 3 Bus Architecture The SoCs employ the ARM Advanced Microcont...

Page 38: ...fer data while the ARM core executes from Tightly Coupled Memory TCM 1 4 Operating Modes The SoCs support three operating modes Normal Mode PLL Bypass Mode Embedded ICE Mode The operating mode that the SoC enters at Power on Reset is determined by the state of the TEST1 TEST2 and nRESETIN signals Table 1 3 shows the signal states that corre spond to each operating mode The TEST1 TEST2 and nRESETIN...

Page 39: ...XTALIN becomes the direct clock input to the RCPC replacing the PLL output The system clock can be scaled down from divide by 30 to divide by 2 During PLL Bypass Mode the TEST2 pin must remain LOW until nPOR is asserted and the operating mode is changed 1 4 3 Embedded ICE Mode In Embedded ICE Mode the JTAG port accesses the TAP Controller in the ARM7 core and the ARM7 core is placed in Debug Mode ...

Page 40: ... come from the VDDC output s In this instance connect VDDA_PLL to VDDC through the filter 1 5 1 2 PCB Mounted Analog Power Supply Filter for PLL Usage Ideally an Analog Power Supply Filter a low pass filter with 3 dB at 1 kHz and 70 dB in the absorption band should be used However real life components limit the 3 dB point A good board layout is vital to achieving good high frequency absorption An ...

Page 41: ...t traces for all applications The leads of the high frequency capacitor must be kept short this includes Board wires Vias Capacitor wires Wires within the capacitor package Therefore select components carefully The area and impedance of the power loop must be minimized where the loop includes the high frequency capacitor and VDDA_PLL and VSSA_PLL board traces to the IC The board layout should have...

Page 42: ...quency require ments of the system 1 7 Clocking Strategy The SoCs provide for two crystal oscillators The first oscillator drives an internal Phased Lock Loop PLL and the three UARTs It supports a frequency range from 10 MHz to 20 MHz and requires a 1 8 V source on its external inputs The second oscillator is a 32 768 kHz oscillator that generates a 1 Hz clock for the RTC The internal PLL multipli...

Page 43: ...by 2 in decrements of two 30 28 26 24 of the XTALIN frequency It can have a maximum system clock frequency of 51 6096 MHz and a minimum of zero as this is a static design The device remains in PLL Bypass Mode until power is removed or nPOR transitions from LOW to HIGH again 1 8 Reset Strategy Two external signals nPOR and nRESETIN generate resets to the SoCs If nPOR is asserted all internal regist...

Page 44: ...s Color and Grayscale LCD Controller 12 bit 4096 Direct Mode Color up to VGA 640 480 8 bit 256 Direct or Palletized Color up to SVGA 800 600 DPI 4 bit 16 Direct Mode Color Grayscale up to XGA 1 024 768 DPI 12 bit Video Bus Supports Supertwist Nematic STN Thin Film Transistor TFT High Reflective TFT HR TFT and Advanced TFT AD TFT Displays Controller Area Network CAN Controller that supports CAN ver...

Page 45: ...riate chapters in this User s Guide Figure 2 1 LH75401 Block Diagram LH75401 1 OSCILLATOR PLL POWER MANAGEMENT and RESET CONTROL VECTORED INTERRUPT CONTROLLER INTERNAL 16KB SRAM TCM 16KB SRAM AHB INTERFACE BROWNOUT DETECTOR LINEAR REGULATOR 14 to 20 MHz 32 768 kHz REAL TIME CLOCK COLOR LCD CONTROLLER STATIC MEMORY CONTROLLER ARM7TDMI S ADVANCED PERIPHERAL BUS BRIDGE 4 CHANNEL DMA CONTROLLER ADVANC...

Page 46: ... machines Refrigerators Cooking equipment Typical industrial control applications include but are not limited to Measuring instruments Machine control systems Programmable Logic Controllers Figure 2 2 shows a system application example for the LH75401 Figure 2 2 LH75401 System Application Example STN TFT AD TFT HR TFT LCD TOUCH SCREEN GPIO SSP A D KEY MATRIX SERIAL EEPROM CAN 2 0B CAN NETWORK A D ...

Page 47: ...TAL32IN nPOR VSSC PD0 INT0 125 126 127 128 129 130 VSS PG4 LCDVEEEN LCDMOD PG3 LCDVDDEN PG2 LCDDSPLEN LCDREV PG1 LCDCLS PG0 LCDPS 119 120 121 122 123 124 PF2 CTCAP0E PF1 CTCAP0D PF0 CTCAP0C PG7 CTCAP0B CTCMP0B PG6 CTCAP0A CTCMP0A PG5 CTCLK 113 114 115 116 117 118 PF5 CTCAP2A CTCMP2A PF4 CTCAP1B CTCMP1B PF3 CTCAP1A CTCMP1A VDD 109 110 111 112 131 132 133 134 135 136 137 138 139 140 141 142 143 144 ...

Page 48: ...round None 15 D5 I O 8 mA Bidirectional 16 D4 I O 8 mA Bidirectional 17 VDD Power None 18 D3 I O 8 mA Bidirectional 19 D2 I O 8 mA Bidirectional 20 D1 I O 8 mA Bidirectional 21 D0 I O 8 mA Bidirectional 22 nWE 8 mA Output 3 23 nOE 8 mA Output 3 24 PB5 nWAIT 8 mA Bidirectional Pull up 1 3 25 PB4 nBLE1 8 mA Bidirectional Pull up 1 3 26 VSS Ground None 27 PB3 nBLE0 8 mA Bidirectional Pull up 1 3 28 P...

Page 49: ...p 2 3 63 TEST2 None Input Pull up 2 64 TEST1 None Input Pull up 2 65 TMS None Input Pull up 2 66 RTCK 8 mA Output 67 TCK None Input 68 TDI None Input Pull up 2 69 TDO 4 mA Output 70 LINREGEN None Input 71 nRESETOUT 8 mA Output 3 72 PD6 INT6 DREQ 6 mA Bidirectional Pull down 1 73 PD5 INT5 DACK 6 mA Bidirectional 1 2 74 PD4 INT4 UARTRX1 8 mA Bidirectional Pull up 1 75 VDDC Power None 76 PD3 INT3 UAR...

Page 50: ...CANTX UARTTX0 8 mA Bidirectional Pull up 1 104 PE2 CANRX UARTRX0 2 mA Bidirectional Pull up 1 105 PE1 UARTTX2 4 mA Bidirectional Pull up 1 106 VSS Ground None 107 PE0 UARTRX2 4 mA Bidirectional Pull up 1 108 PF6 CTCAP2B CTCMP2B 4 mA Bidirectional 2 109 PF5 CTCAP2A CTCMP2A 4 mA Bidirectional 110 PF4 CTCAP1B CACMP1B 4 mA Bidirectional 2 111 PF3 CTCAP1A CTCMP1A 4 mA Bidirectional 112 VDD Power None 1...

Page 51: ...LCDFP LCDSPS 8 mA Bidirectional 130 PH4 LCDEN LCDSPL 8 mA Bidirectional 131 PH3 LCDVD11 8 mA Bidirectional 132 PH2 LCDVD10 8 mA Bidirectional 133 PH1 LCDVD9 8 mA Bidirectional 134 VDD Power None 135 PH0 LCDVD8 8 mA Bidirectional 136 PI7 LCDVD7 8 mA Bidirectional 137 PI6 LCDVD6 8 mA Bidirectional 138 PI5 LCDVD5 8 mA Bidirectional 139 PI4 LCDVD4 8 mA Bidirectional 140 VSS Ground None 141 PI3 LCDVD3 ...

Page 52: ... 24 nWAIT Input Static Memory Controller External Wait Control 1 2 25 nBLE1 Output Static Memory Controller Byte Lane Strobe 1 2 27 nBLE0 Output Static Memory Controller Byte Lane Strobe 1 2 28 nCS3 Output Static Memory Controller Chip Select 1 2 29 nCS2 Output Static Memory Controller Chip Select 1 2 30 nCS1 Output Static Memory Controller Chip Select 1 2 31 nCS0 Output Static Memory Controller C...

Page 53: ...gnal that Resets the Row Driver Counter HR TFT only 1 130 LCDEN Output LCD Data Enable 1 130 LCDSPL Output HR TFT Start Pulse Left HR TFT only 1 131 132 133 135 136 137 138 139 141 142 143 144 LCDVD 11 0 Output LCD Panel Data bus 1 SYNCHRONOUS SERIAL PORT SSP 99 SSPFRM Input SSP Serial Frame 1 100 SSPCLK Input SSP Clock 1 101 SSPRX Input SSP RXD 1 102 SSPTX Output SSP TXD 1 UART0 U0 103 UARTTX0 Ou...

Page 54: ... Output Timer 1 Compare Outputs 1 118 CTCLK Input Common External Clock 1 TIMER 2 109 108 CTCAP2 A B Input Timer 2 Capture Inputs 1 109 108 CTCMP2 A B Input Timer 2 Compare Outputs 1 118 CTCLK Input Common External Clock 1 GENERAL PURPOSE INPUT OUTPUT GPIO 1 2 4 5 6 7 9 10 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Input Output General Purpose I O Signals Port A 1 24 25 27 28 29 30 PB5 PB4 PB3 PB2 PB1 PB0 In...

Page 55: ...nput Output General Purpose I O Signals Port F 1 116 117 118 120 121 122 123 124 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 Input Output General Purpose I O Signals Port G 1 125 128 129 130 131 132 133 135 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 Input Output General Purpose I O Signals Port H 1 136 137 138 139 141 142 143 144 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 Input Output General Purpose I O Signals Port I 1 RESET CLO...

Page 56: ...Output TEST INTERFACE 63 TEST2 Input Test Mode Pin 2 64 TEST1 Input Test Mode Pin 1 65 TMS Input JTAG Test Mode Select Input 66 RTCK Output Returned JTAG Test Clock Output 67 TCK Input JTAG Test Clock Input 68 TDI Input JTAG Test Serial Data Input 69 TDO Output JTAG Test Data Serial Output POWER AND GROUND GND 3 17 34 42 54 98 112 126 134 VDD Power I O Ring VDD 8 26 41 48 59 106 119 127 140 VSS Po...

Page 57: ...olor and Grayscale LCD Controller 12 bit 4096 Direct Mode Color up to VGA 640 480 Dots per Inch 8 bit 256 Direct or Palletized Color up to SVGA 800 x 600 DPI 4 bit 16 Direct Mode Color Grayscale up to XGA 1024 x 768 DPI 12 bit Video Bus Supports Supertwist Nematic STN Thin Film Transistor TFT High Reflective TFT HR TFT and Advanced TFT AD TFT Displays Serial interfaces Two 16C550 type UARTs One 82...

Page 58: ...gram LH75411 1 OSCILLATOR PLL POWER MANAGEMENT and RESET CONTROL VECTORED INTERRUPT CONTROLLER INTERNAL 16KB SRAM TCM 16KB SRAM AHB INTERFACE BROWNOUT DETECTOR LINEAR REGULATOR 14 to 20 MHz 32 768 kHz REAL TIME CLOCK COLOR LCD CONTROLLER STATIC MEMORY CONTROLLER ARM 7TDMI S ADVANCED PERIPHERAL BUS BRIDGE 4 CHANNEL DMA CONTROLLER ADVANCED HIGH PERFORMANCE BUS AHB ADVANCED PERPHERAL BUS APB AD TFT L...

Page 59: ...ng machines Refrigerators Cooking equipment Typical industrial control applications include but are not limited to Measuring instruments Machine control systems Program logic controllers Figure 3 2 shows a system application example for the LH75411 Figure 3 2 LH75411 System Application Example STN TFT AD TFT HR TFT LCD TOUCH SCREEN GPIO SSP A D KEY MATRIX SERIAL EEPROM CAN 2 0B CAN NETWORK A D FLA...

Page 60: ...N nPOR VSSC PD0 INT0 125 126 127 128 129 130 VSS PG4 LCDVEEEN LCDMOD PG3 LCDVDDEN PG2 LCDDSPLEN LCDREV PG1 LCDCLS PG0 LCDPS 119 120 121 122 123 124 PF2 CTCAP0E PF1 CTCAP0D PF0 CTCAP0C PG7 CTCAP0B CTCMP0B PG6 CTCAP0A CTCMP0A PG5 CTCLK 113 114 115 116 117 118 PF5 CTCAP2A CTCMP2A PF4 CTCAP1B CTCMP1B PF3 CTCAP1A CTCMP1A VDD 109 110 111 112 131 132 133 134 135 136 137 138 139 140 141 142 143 144 92 90 ...

Page 61: ...ound None 15 D5 I O 8 mA Bidirectional 16 D4 I O 8 mA Bidirectional 17 VDD Power None 18 D3 I O 8 mA Bidirectional 19 D2 I O 8 mA Bidirectional 20 D1 I O 8 mA Bidirectional 21 D0 I O 8 mA Bidirectional 22 nWE 8 mA Output 3 23 nOE 8 mA Output 3 24 PB5 nWAIT 8 mA Bidirectional Pull up 1 3 25 PB4 nBLE1 8 mA Bidirectional Pull up 1 3 26 VSS Ground None 27 PB3 nBLE0 8 mA Bidirectional Pull up 1 3 28 PB...

Page 62: ...p 2 3 63 TEST2 None Input Pull up 2 64 TEST1 None Input Pull up 2 65 TMS None Input Pull up 2 66 RTCK 8 mA Output 67 TCK None Input 68 TDI None Input Pull up 2 69 TDO 4 mA Output 70 LINREGEN None Input 71 nRESETOUT 8 mA Output 3 72 PD6 INT6 DREQ 6 mA Bidirectional Pull down 1 73 PD5 INT5 DACK 6 mA Bidirectional 1 2 74 PD4 INT4 UARTRX1 8 mA Bidirectional Pull up 1 75 VDDC Power None 76 PD3 INT3 UAR...

Page 63: ... PE3 UARTTX0 8 mA Bidirectional Pull up 1 104 PE2 UARTRX0 2 mA Bidirectional Pull up 1 105 PE1 UARTTX2 4 mA Bidirectional Pull up 1 106 VSS Ground None 107 PE0 UARTRX2 4 mA Bidirectional Pull up 1 108 PF6 CTCAP2B CTCMP2B 4 mA Bidirectional 2 109 PF5 CTCAP2A CTCMP2A 4 mA Bidirectional 110 PF4 CTCAP1B CACMP1B 4 mA Bidirectional 2 111 PF3 CTCAP1A CTCMP1A 4 mA Bidirectional 112 VDD Power None 113 PF2 ...

Page 64: ...CDFP LCDSPS 8 mA Bidirectional 130 PH4 LCDEN LCDSPL 8 mA Bidirectional 131 PH3 LCDVD11 8 mA Bidirectional 132 PH2 LCDVD10 8 mA Bidirectional 133 PH1 LCDVD9 8 mA Bidirectional 134 VDD Power None 135 PH0 LCDVD8 8 mA Bidirectional 136 PI7 LCDVD7 8 mA Bidirectional 137 PI6 LCDVD6 8 mA Bidirectional 138 PI5 LCDVD5 8 mA Bidirectional 139 PI4 LCDVD4 8 mA Bidirectional 140 VSS Ground None 141 PI3 LCDVD3 8...

Page 65: ...24 nWAIT Input Static Memory Controller External Wait Control 1 2 25 nBLE1 Output Static Memory Controller Byte Lane Strobe 1 2 27 nBLE0 Output Static Memory Controller Byte Lane Strobe 1 2 28 nCS3 Output Static Memory Controller Chip Select 1 2 29 nCS2 Output Static Memory Controller Chip Select 1 2 30 nCS1 Output Static Memory Controller Chip Select 1 2 31 nCS0 Output Static Memory Controller Ch...

Page 66: ...nal that Resets the Row Driver Counter HR TFT only 1 130 LCDEN Output LCD Data Enable 1 130 LCDSPL Output HR TFT Start Pulse Left HR TFT only 1 131 132 133 135 136 137 138 139 141 142 143 144 LCDVD 11 0 Output LCD Panel Data bus 1 SYNCHRONOUS SERIAL PORT SSP 99 SSPFRM Input SSP Serial Frame 1 100 SSPCLK Input SSP Clock 1 101 SSPRX Input SSP RXD 1 102 SSPTX Output SSP TXD 1 UART0 U0 104 UARTRX0 Inp...

Page 67: ...pture Inputs 1 109 108 CTCMP2 A B Input Timer 2 Compare Outputs 1 118 CTCLK Input Common External Clock 1 GENERAL PURPOSE INPUT OUTPUT GPIO 1 2 4 5 6 7 9 10 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Input Output General Purpose I O Signals Port A 1 24 25 27 28 29 30 PB5 PB4 PB3 PB2 PB1 PB0 Input Output General Purpose I O Signals Port B 1 32 33 35 36 37 38 39 40 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Input Output ...

Page 68: ... G 1 125 128 129 130 131 132 133 135 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 Input Output General Purpose I O Signals Port H 1 136 137 138 139 141 142 143 144 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 Input Output General Purpose I O Signals Port I 1 RESET CLOCK AND POWER CONTROLLER RCPC 62 nRESETIN Input User Reset Input 2 71 nRESETOUT Output System Reset Output 2 72 INT6 Input External Interrupt Input 6 1 73 INT5...

Page 69: ...ode Select Input 66 RTCK Output Returned JTAG Test Clock Output 67 TCK Input JTAG Test Clock Input 68 TDI Input JTAG Test Serial Data Input 69 TDO Output JTAG Test Data Serial Output POWER AND GROUND GND 3 17 34 42 54 98 112 126 134 VDD Power I O Ring VDD 8 26 41 48 59 106 119 127 140 VSS Power I O Ring VSS 11 75 VDDC Power Core VDD supply Output if Linear Regulator Enabled Otherwise Input 14 80 V...

Page 70: ...tegrated Touch Screen Controller Four DMA Channels Grayscale LCD Controller 4 bit 16 Level Grayscale up to XGA 1024 768 8 bit Video Bus Supports STN Displays CAN Controller that supports CAN version 2 0B Serial interfaces Two 16C550 type UARTs One 82510 type UART Synchronous Serial Port SSP Motorola SPI National Semiconductor Microwire Texas Instruments SSI Real Time Clock RTC Three Counter Timers...

Page 71: ...EMENT and RESET CONTROL VECTORED INTERRUPT CONTROLLER INTERNAL 16KB SRAM TCM 16KB SRAM AHB INTERFACE BROWNOUT DETECTOR LINEAR REGULATOR 14 to 20 MHz 32 768 kHz REAL TIME CLOCK GRAYSCALE LCD CONTROLLER STATIC MEMORY CONTROLLER ARM 7TDMI S ADVANCED PERIPHERAL BUS BRIDGE 4 CHANNEL DMA CONTROLLER ADVANCED HIGH PERFORMANCE BUS AHB ADVANCED PERPHERAL BUS APB 76 BIT GENERAL PURPOSE I O I O CONFIGURATION ...

Page 72: ...ers Washing machines Refrigerators Cooking equipment Typical industrial control applications include but are not limited to Measuring instruments Machine control systems Program logic controllers Figure 4 2 shows a system application example for the LH75400 Figure 4 2 LH75400 System Application Example STN LCD TOUCH SCREEN GPIO SPI A D KEY MATRIX SERIAL EEPROM CAN 2 0B CAN NETWORK A D FLASH SRAM B...

Page 73: ...PJ4 AN9 PJ5 AN4 WIPER PJ6 AN3 LR Y PJ7 VSSA_ADC XTALOUT XTALIN VDDA_PLL VSSA_PLL XTAL32OUT XTAL32IN nPOR VSSC PD0 INT0 125 126 127 128 129 130 VSS PG4 LCDVEEEN PG3 LCDVDDEN PG2 LCDDSPLEN PG1 PG0 119 120 121 122 123 124 PF2 CTCAP0E PF1 CTCAP0D PF0 CTCAP0C PG7 CTCAP0B CTCMP0B PG6 CTCAP0A CTCMP0A PG5 CTCLK 113 114 115 116 117 118 PF5 CTCAP2A CTCMP2A PF4 CTCAP1B CTCMP1B PF3 CTCAP1A CTCMP1A VDD 109 110...

Page 74: ...ound None 15 D5 I O 8 mA Bidirectional 16 D4 I O 8 mA Bidirectional 17 VDD Power None 18 D3 I O 8 mA Bidirectional 19 D2 I O 8 mA Bidirectional 20 D1 I O 8 mA Bidirectional 21 D0 I O 8 mA Bidirectional 22 nWE 8 mA Output 3 23 nOE 8 mA Output 3 24 PB5 nWAIT 8 mA Bidirectional Pull up 1 3 25 PB4 nBLE1 8 mA Bidirectional Pull up 1 3 26 VSS Ground None 27 PB3 nBLE0 8 mA Bidirectional Pull up 1 3 28 PB...

Page 75: ...p 2 3 63 TEST2 None Input Pull up 2 64 TEST1 None Input Pull up 2 65 TMS None Input Pull up 2 66 RTCK 8 mA Output 67 TCK None Input 68 TDI None Input Pull up 2 69 TDO 4 mA Output 70 LINREGEN None Input 71 nRESETOUT 8 mA Output 3 72 PD6 INT6 DREQ 6 mA Bidirectional Pull down 1 73 PD5 INT5 DACK 6 mA Bidirectional 1 2 74 PD4 INT4 UARTRX1 8 mA Bidirectional Pull up 1 75 VDDC Power None 76 PD3 INT3 UAR...

Page 76: ...E3 CANTX UARTTX0 8 mA Bidirectional Pull up 1 104 PE2 CANRX UARTRX0 2 mA Bidirectional Pull up 1 105 PE1 UARTTX2 4 mA Bidirectional Pull up 1 106 VSS Ground None 107 PE0 UARTRX2 4 mA Bidirectional Pull up 1 108 PF6 CTCAP2B CTCMP2B 4 mA Bidirectional 2 109 PF5 CTCAP2A CTCMP2A 4 mA Bidirectional 110 PF4 CTCAP1B CACMP1B 4 mA Bidirectional 2 111 PF3 CTCAP1A CTCMP1A 4 mA Bidirectional 112 VDD Power Non...

Page 77: ...mA Bidirectional 130 PH4 LCDEN 8 mA Bidirectional 131 PH3 LCDVD11 8 mA Bidirectional 132 PH2 LCDVD10 8 mA Bidirectional 133 PH1 LCDVD9 8 mA Bidirectional 134 VDD Power None 135 PH0 LCDVD8 8 mA Bidirectional 136 PI7 LCDVD7 8 mA Bidirectional 137 PI6 LCDVD6 8 mA Bidirectional 138 PI5 LCDVD5 8 mA Bidirectional 139 PI4 LCDVD4 8 mA Bidirectional 140 VSS Ground None 141 PI3 LCDVD3 8 mA Bidirectional 142...

Page 78: ...24 nWAIT Input Static Memory Controller External Wait Control 1 2 25 nBLE1 Output Static Memory Controller Byte Lane Strobe 1 2 27 nBLE0 Output Static Memory Controller Byte Lane Strobe 1 2 28 nCS3 Output Static Memory Controller Chip Select 1 2 29 nCS2 Output Static Memory Controller Chip Select 1 2 30 nCS1 Output Static Memory Controller Chip Select 1 2 31 nCS0 Output Static Memory Controller Ch...

Page 79: ...ial Frame 1 100 SSPCLK Input SSP Clock 1 101 SSPRX Input SSP RXD 1 102 SSPTX Output SSP TXD 1 UART0 U0 103 UARTTX0 Output UART0 Transmitted Serial Data Output 1 104 UARTRX0 Input UART0 Received Serial Data Input 1 UART1 U1 74 UARTRX1 Input UART1 Received Serial Data Input 1 76 UARTTX1 Output UART1 Transmitted Serial Data Output 1 UART2 U2 105 UARTTX2 Output UART2 Transmitted Serial Data Output 1 1...

Page 80: ...pture Inputs 1 109 108 CTCMP2 A B Input Timer 2 Compare Outputs 1 118 CTCLK Input Common External Clock 1 GENERAL PURPOSE INPUT OUTPUT GPIO 1 2 4 5 6 7 9 10 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Input Output General Purpose I O Signals Port A 1 24 25 27 28 29 30 PB5 PB4 PB3 PB2 PB1 PB0 Input Output General Purpose I O Signals Port B 1 32 33 35 36 37 38 39 40 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Input Output ...

Page 81: ... G 1 125 128 129 130 131 132 133 135 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 Input Output General Purpose I O Signals Port H 1 136 137 138 139 141 142 143 144 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 Input Output General Purpose I O Signals Port I 1 RESET CLOCK AND POWER CONTROLLER RCPC 62 nRESETIN Input User Reset Input 2 71 nRESETOUT Output System Reset Output 2 72 INT6 Input External Interrupt Input 6 1 73 INT5...

Page 82: ...ode Select Input 66 RTCK Output Returned JTAG Test Clock Output 67 TCK Input JTAG Test Clock Input 68 TDI Input JTAG Test Serial Data Input 69 TDO Output JTAG Test Data Serial Output POWER AND GROUND GND 3 17 34 42 54 98 112 126 134 VDD Power I O Ring VDD 8 26 41 48 59 106 119 127 140 VSS Power I O Ring VSS 11 75 VDDC Power Core VDD supply Output if Linear Regulator Enabled Otherwise Input 14 80 V...

Page 83: ...10 bit A D Converter Integrated Touch Screen Controller Four DMA Channels Grayscale LCD Controller 4 bit 16 Level Grayscale up to XGA 1024 768 8 bit Video Bus Supports STN Displays Serial interfaces Two 16C550 type UARTs One 82510 type UART Synchronous Serial Port SSP Motorola SPI National Semiconductor Microwire Texas Instruments SSI Real Time Clock RTC Three Counter Timers Capture Compare PWM Co...

Page 84: ...MANAGEMENT and RESET CONTROL VECTORED INTERRUPT CONTROLLER INTERNAL 16KB SRAM TCM 16KB SRAM AHB INTERFACE BROWNOUT DETECTOR LINEAR REGULATOR 14 to 20 MHz 32 768 kHz REAL TIME CLOCK GRAYSCALE LCD CONTROLLER STATIC MEMORY CONTROLLER ARM 7TDMI S ADVANCED PERIPHERAL BUS BRIDGE 4 CHANNEL DMA CONTROLLER ADVANCED HIGH PERFORMANCE BUS AHB ADVANCED PERPHERAL BUS APB 76 BIT GENERAL PURPOSE I O I O CONFIGURA...

Page 85: ...d to Air conditioners Washing machines Refrigerators Cooking equipment Typical industrial control applications include but are not limited to Measuring instruments Machine control systems Program logic controllers Figure 5 2 shows a system application example for the LH75410 Figure 5 2 LH75410 System Application Example STN LCD TOUCH SCREEN GPIO SSP A D KEY MATRIX SERIAL EEPROM A D FLASH SRAM BOOT...

Page 86: ...C PD0 INT0 125 126 127 128 129 130 VSS PG4 LCDVEEEN PG3 LCDVDDEN PG2 LCDDSPLEN PG1 PG0 119 120 121 122 123 124 PF2 CTCAP0E PF1 CTCAP0D PF0 CTCAP0C PG7 CTCAP0B CTCMP0B PG6 CTCAP0A CTCMP0A PG5 CTCLK 113 114 115 116 117 118 PF5 CTCAP2A CTCMP2A PF4 CTCAP1B CTCMP1B PF3 CTCAP1A CTCMP1A VDD 109 110 111 112 131 132 133 134 135 136 137 138 139 140 141 142 143 144 92 90 89 88 87 86 85 84 83 82 81 80 79 105 ...

Page 87: ...SSC Ground None 15 D5 I O 8 mA Bidirectional 16 D4 I O 8 mA Bidirectional 17 VDD Power None 18 D3 I O 8 mA Bidirectional 19 D2 I O 8 mA Bidirectional 20 D1 I O 8 mA Bidirectional 21 D0 I O 8 mA Bidirectional 22 nWE 8 mA Output 3 23 nOE 8 mA Output 3 24 PB5 nWAIT 8 mA Bidirectional Pull up 1 25 PB4 nBLE1 8 mA Bidirectional Pull up 1 26 VSS Ground None 27 PB3 nBLE0 8 mA Bidirectional Pull up 1 28 PB...

Page 88: ...p 2 3 63 TEST2 None Input Pull up 2 64 TEST1 None Input Pull up 2 65 TMS None Input Pull up 2 66 RTCK 8 mA Output 67 TCK None Input 68 TDI None Input Pull up 2 69 TDO 4 mA Output 70 LINREGEN None Input 71 nRESETOUT 8 mA Output 3 72 PD6 INT6 DREQ 6 mA Bidirectional Pull down 1 73 PD5 INT5 DACK 6 mA Bidirectional 1 2 74 PD4 INT4 UARTRX1 8 mA Bidirectional Pull up 1 75 VDDC Power None 76 PD3 INT3 UAR...

Page 89: ... 103 PE3 UARTTX0 8 mA Bidirectional Pull up 1 104 PE2 UARTRX0 2 mA Bidirectional Pull up 1 105 PE1 UARTTX2 4 mA Bidirectional Pull up 1 106 VSS Ground None 107 PE0 UARTRX2 4 mA Bidirectional Pull up 1 108 PF6 CTCAP2B CTCMP2B 4 mA Bidirectional 2 109 PF5 CTCAP2A CTCMP2A 4 mA Bidirectional 110 PF4 CTCAP1B CACMP1B 4 mA Bidirectional 2 111 PF3 CTCAP1A CTCMP1A 4 mA Bidirectional 112 VDD Power None 113 ...

Page 90: ...mA Bidirectional 130 PH4 LCDEN 8 mA Bidirectional 131 PH3 LCDVD11 8 mA Bidirectional 132 PH2 LCDVD10 8 mA Bidirectional 133 PH1 LCDVD9 8 mA Bidirectional 134 VDD Power None 135 PH0 LCDVD8 8 mA Bidirectional 136 PI7 LCDVD7 8 mA Bidirectional 137 PI6 LCDVD6 8 mA Bidirectional 138 PI5 LCDVD5 8 mA Bidirectional 139 PI4 LCDVD4 8 mA Bidirectional 140 VSS Ground None 141 PI3 LCDVD3 8 mA Bidirectional 142...

Page 91: ...24 nWAIT Input Static Memory Controller External Wait Control 1 2 25 nBLE1 Output Static Memory Controller Byte Lane Strobe 1 2 27 nBLE0 Output Static Memory Controller Byte Lane Strobe 1 2 28 nCS3 Output Static Memory Controller Chip Select 1 2 29 nCS2 Output Static Memory Controller Chip Select 1 2 30 nCS1 Output Static Memory Controller Chip Select 1 2 31 nCS0 Output Static Memory Controller Ch...

Page 92: ...P Serial Frame 1 100 SSPCLK Input SSP Clock 1 101 SSPRX Input SSP RXD 1 102 SSPTX Output SSP TXD 1 UART0 U0 103 UARTTX0 Output UART0 Transmitted Serial Data Output 1 104 UARTRX0 Input UART0 Received Serial Data Input 1 UART1 U1 74 UARTRX1 Input UART1 Received Serial Data Input 1 76 UARTTX1 Output UART1 Transmitted Serial Data Output 1 UART2 U2 105 UARTTX2 Output UART2 Transmitted Serial Data Outpu...

Page 93: ...RAL PURPOSE INPUT OUTPUT GPIO 1 2 4 5 6 7 9 10 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Input Output General Purpose I O Signals Port A 1 24 25 27 28 29 30 PB5 PB4 PB3 PB2 PB1 PB0 Input Output General Purpose I O Signals Port B 1 32 33 35 36 37 38 39 40 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Input Output General Purpose I O Signals Port C 1 72 73 74 76 77 78 79 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Input Output General Pur...

Page 94: ...1 PI0 Input Output General Purpose I O Signals Port I 1 RESET CLOCK AND POWER CONTROLLER RCPC 62 nRESETIN Input User Reset Input 2 71 nRESETOUT Output System Reset Output 2 72 INT6 Input External Interrupt Input 6 1 73 INT5 Input External Interrupt Input 5 1 74 INT4 Input External Interrupt Input 4 1 76 INT3 Input External Interrupt Input 3 1 77 INT2 Input External Interrupt Input 2 1 78 INT1 Inpu...

Page 95: ...a Input 69 TDO Output JTAG Test Data Serial Output POWER AND GROUND GND 3 17 34 42 54 98 112 126 134 VDD Power I O Ring VDD 8 26 41 48 59 106 119 127 140 VSS Power I O Ring VSS 11 75 VDDC Power Core VDD supply Output if Linear Regulator Enabled Otherwise Input 14 80 VSSC Power Core VSS 70 LINREGEN Input Linear Regulator Enable 84 VSSA_PLL Power PLL Analog VSS 85 VDDA_PLL Power PLL Analog VDD Suppl...

Page 96: ...uch as System configuration registers Peripheral configuration registers TCM and internal SRAM The first partitioning of memory space is its subdivision into eight segments Each seg ment spans 512MB The start address of each segment is fixed and determined by the three highest order bits of the 32 bit AHB address These segments define the type of resource being addressed For example One segment ca...

Page 97: ...s reserved and will cause any access to lower memory to result in a memory abort 6 Do not specify TCM as either the frame buffer or as the source or destination for DMA transfers Setting REMAP 01 causes TCM to be aliased to the address range 0x00000000 0x00003FFF Exercise care when setting DMA transfer or frame buffer addresses to that address range Note that the UPBASE and LPBASE Registers must a...

Page 98: ...esents a valid REMAP value 00 01 or 10 Table 6 2 External Memory Section Mapping START ADDRESS DEVICE REMAP XX REMAP 00 0x40000000 0x00000000 Chip Select 0 0x44000000 0x04000000 Chip Select 1 0x48000000 0x08000000 Chip Select 2 0x4C000000 0x0C000000 Chip Select 3 0x50000000 0x10000000 Invalid Access 0x54000000 0x14000000 Invalid Access 0x58000000 0x18000000 Invalid Access 0x5C000000 0x1C000000 Inv...

Page 99: ... LH75401 and LH75400 Reserved LH75411 and LH75410 0xFFFC6000 0xFFFC6FFF Synchronous Serial Port 0xFFFC7000 0xFFFDAFFF Reserved 0xFFFDB000 0xFFFDBFFF GPIO4 0xFFFDC000 0xFFFDCFFF GPIO3 0xFFFDD000 0xFFFDDFFF GPIO2 0xFFFDE000 0xFFFDEFFF GPIO1 0xFFFDF000 0xFFFDFFFF GPIO0 0xFFFE0000 0xFFFE0FFF Real Time Clock 0xFFFE1000 0xFFFE1FFF DMA Controller 0xFFFE2000 0xFFFE2FFF Reset Clock and Power Controller 0xF...

Page 100: ...emory bank 7 1 SMC Features The SMC is programmed through the AHB Each memory bank has its own Configuration Register SMCBCR 3 0 This register allows each bank to be configured independently to Support memory mapped devices including Random Access Memory RAM ROM Flash and burst ROM Vary the external bus width 8 or 16 bits wide Vary the external device width 8 or 16 bits wide Asynchronous Burst Mod...

Page 101: ... to ensure cor rect operation of the external memories Rather timing relationships are ensured by timing the interface signals with the System Clock signal This approach makes the tim ing characteristics of the interface dependent on the clock rates used 3 The SMC immediately places address bits 23 0 on the external A 23 0 address bus At the same time it receives the write data from the AHB Being ...

Page 102: ... User s Guide Static Memory Controller 6 17 03 7 3 Figure 7 1 SMC Write Access HCLK HADDR 31 0 INTERNAL SIGNALS HWDATA 31 0 A 23 0 D 15 0 nBLE 1 0 nWEN nWAIT nCSx HWRITE HREADY DATA ADDRESS DATA ADDRESS LH754xx 5 EXTERNAL SIGNALS ...

Page 103: ...s the SMC holds this state for either N clock cycles or until nWAIT is sampled as being inactive whichever happens last The SMC captures the data on the following edge of the system clock following the assertion of nCSx The nCSx signal and the address are removed one cycle later If the external mem ory interface is not as wide as the AHB transfer request the SMC issues successive exter nal read bu...

Page 104: ...r s Guide Static Memory Controller 6 17 03 7 5 Figure 7 2 SMC Write nCSx De asserted Early HCLK HADDR 31 0 INTERNAL SIGNALS HWDATA 31 0 A 23 0 D 15 0 nBLE 1 0 nWEN nWAIT nCSx HWRITE HREADY DATA DATA ADDRESS LH754xx 53 EXTERNAL SIGNALS ...

Page 105: ...75400 01 10 11 Preliminary User s Guide 7 6 6 17 03 Figure 7 3 SMC Read Access HCLK HADDR 31 0 D 15 0 nXCS x nXOEN A 23 0 HRDATA 31 0 nWAIT HWRITE DATA DATA ADDRESS 1 WAIT STATE ADDRESS LH754xx 6 INTERNAL SIGNALS EXTERNAL SIGNALS ...

Page 106: ...ller 6 17 03 7 7 Figure 7 4 SMC Burst Read Access 2 WAIT STATES 0x00000000 DATA ADDRESS A 3 DATA A 3 ADDRESS A 2 ADDRESS A 1 ADDRESS A DATA A 2 DATA A 1 DATA A 0 WAIT STATES HCLK HRDATA 31 0 D 15 0 nCSx nWAIT nOE A 23 0 LH754xx 7 INTERNAL SIGNALS EXTERNAL SIGNALS ...

Page 107: ... ing reads The SMC performs the mapping to ensure that each byte read is at the correct location in the system bus During writes the nBLE 1 0 signals Ensure that only the external device in a memory bank for which the data is intended will perform the write Direct the device to steer the data to the correct portion of its memory if the external device is wider than the data As this shows the SMC c...

Page 108: ...ad ACCESS READ 8 BIT EXTERNAL BUS EXTERNAL DATA MAPPING ONTO AHB DATA BUS INTERNAL TRANSFER WIDTH HSIZE 1 0 HADDR 1 0 A 1 0 31 24 23 16 15 8 7 0 Word 4 transfers 10 10 10 10 xx xx xx xx 11 10 01 00 7 0 7 0 7 0 7 0 Halfword 2 transfers 01 1x 11 10 7 0 7 0 Halfword 2 transfers 01 0x 01 00 7 0 Byte 00 11 11 7 0 Byte 00 10 10 7 0 Byte 00 01 01 7 0 Byte 00 00 00 7 0 Table 7 4 16 bit External Bus Read A...

Page 109: ...rs 01 1x 11 10 10 10 31 24 23 16 Halfword 2 transfers 01 0x 01 00 10 10 15 8 7 0 Byte 00 11 11 10 31 24 Byte 00 10 10 10 23 16 Byte 00 01 01 10 15 8 Byte 00 00 00 10 7 0 Table 7 6 16 bit External Bus Write ACCESS WRITE 16 BIT EXTERNAL BUS SYSTEM DATA MAPPING ONTO EXTERNAL DATA BUS INTERNAL TRANSFER WIDTH HSIZE 1 0 HADDR 1 0 A 1 0 nBLE 1 0 15 8 7 0 Word 2 transfers 10 10 xx xx 1x 0x 00 00 31 24 15 ...

Page 110: ...stem with different data width memory devices Figure 7 5 Typical Memory Connection Diagram LH754xx 8 A 20 0 Q 31 0 D 15 0 D 15 0 2M 16 BURST MASK ROM nCE nOE A 15 0 IO 15 0 D 15 0 A 16 1 A 23 1 nCS0 nCS1 nWE nCS2 nOE nBLE1 nBLE0 A 21 1 A 16 0 IO 7 0 D 15 8 nCE nOE nWE A 17 1 A 16 0 IO 7 0 D 7 0 nCE nOE nWE A 17 1 64K 16 SRAM 128K 8 SRAM 128K 8 SRAM nCE nOE nWE nUB nLB ...

Page 111: ...n Reset Bank 0 defaults to a 16 bit memory width If PD2 INT2 is pulled LOW on Reset Bank 0 defaults to an 8 bit memory width Table 7 7 SMC Memory Bank Address Space ADDRESS DESCRIPTION SMC MemBase 0x00000000 SMC Memory Bank 0 SMC MemBase 0x04000000 SMC Memory Bank 1 SMC MemBase 0x08000000 SMC Memory Bank 2 SMC MemBase 0x0C000000 SMC Memory Bank 3 Table 7 8 SMC Register Summary NAME ADDRESS OFFSET ...

Page 112: ...0 0 0 0 0 0 RW R R RW RW RW RW RW RW R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD WST2 RBLE WST1 IDCY RESET 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 RW RW RW RW RW RW RW RW RW RW RW RW R RW RW RW RW ADDR 0xFFFF1000 0x00 Table 7 10 BCR0 Register 8 bit Mode BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD MW BM WP WPERR BUSERR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R RW RW RW ...

Page 113: ... read 15 11 WST2 Wait State2 For SRAM WST2 is the write access time burst access time for burst ROM The wait state time is WST2 1 tHCLK For Burst ROM WST2 is the burst access time This wait state time is WST2 tHCLK WaitState2 does not apply to on burst ROM devices Default 11111 10 RBLE Read Byte Lane Enable 2 0 All byte lane strobes nBLE 1 0 held HIGH during reads from off chip memory default at S...

Page 114: ...SCRIPTION 31 30 Reserved Do not write Must be set to 00 Unpredictable behavior if set to any other value Read as zero 29 28 MW Memory Width 00 8 bit 01 16 bit 10 Reserved 11 Reserved The MW field defaults to different values for each memory bank at reset See Table 7 18 27 BM Burst Mode 0 Non burst devices Default 1 Burst ROM 26 WP Write Protect 0 SRAM not write protected Default 1 ROM burst ROM an...

Page 115: ... any system reads or writes from memory RBLE is written 0 when interfacing to external 8 bit or non byte partitioned memory devices When RBLE is 0 use nOE for read operations and nBLE 1 0 for write operations nWE is not used When RBLE is 1 use nOE for read op erations and nBLE 1 0 and nWE and nBLE 1 0 for write operations 9 5 WST1 Wait State1 For SRAM and ROM WST1 is the read access time burst acc...

Page 116: ...SCRIPTION 31 30 Reserved Do not write Must be set to 00 Unpredictable behavior if set to any other value Read as zero 29 28 MW Memory Width 00 8 bit 01 16 bit 10 Reserved 11 Reserved The MW field defaults to different values for each memory bank at reset See Table 7 18 27 BM Burst Mode 0 Non burst devices Default 1 Burst ROM 26 WP Write Protect 0 SRAM not write protected Default 1 ROM burst ROM an...

Page 117: ... any system reads or writes from memory RBLE is written 0 when interfacing to external 8 bit or non byte partitioned memory devices When RBLE is 0 use nOE for read operations and nBLE 1 0 for write operations nWE is not used When RBLE is 1 use nOE for read op erations and nBLE 1 0 and nWE and nBLE 1 0 for write operations 9 5 WST1 Wait State1 For SRAM and ROM WST1 is the read access time burst acc...

Page 118: ...ESCRIPTION 31 30 Reserved Do not write Must be set to 00 Unpredictable behavior if set to any other value Read as zero 29 28 MW Memory Width 00 8 bit 01 16 bit 10 Reserved 11 Reserved The MW field defaults to different values for each memory bank at reset See Table 7 18 27 BM Burst Mode 0 Non burst device Default 1 Burst ROM 26 WP Write Protect 0 SRAM not write protected Default 1 ROM burst ROM an...

Page 119: ... any system reads or writes from memory RBLE is written 0 when interfacing to external 8 bit or non byte partitioned memory devices When RBLE is 0 use nOE for read operations and nBLE 1 0 for write operations nWE is not used When RBLE is 1 use nOE for read op erations and nBLE 1 0 and nWE and nBLE 1 0 for write operations 9 5 WST1 Wait State1 For SRAM and ROM WST1 is the read access time burst acc...

Page 120: ...s to a 16 bit memory width If PD2 INT2 is pulled LOW on reset Bank 0 defaults to an 8 bit memory width Pin PD2 INT2 has an internal pull up resistor that selects Bank 0 to be 16 bit unless an external pull down resistor is used on that pin NOTE If PD2 INT2 is LOW while in a Power Down Mode the internal pull up resistor will have a DC current path and deplete the battery Table 7 18 SMC System Reset...

Page 121: ...upled Memory TCM 0 Wait State SRAM is available to the proces sor as an ARM7TDMI S bus slave 16KB of internal SRAM is available as an AHB slave and accessible via processor DMA Controller and LCD Controller Each memory segment is 512MB in size though the TCM and internal SRAMs are 16KB each in size Any access beyond the first 16KB is mapped to the lower 16KB but does not cause a data abort nor a p...

Page 122: ...TERS 14 7456 MHz OSCILLATOR 32 768 kHz OSCILLATOR PLL CLOCK EXTERNAL RESET WDT RESET INPUTS GLOBAL RTC EXTERNAL RESET OUTPUTS EXT ASYNCHRONOUS INTERRUPT INPUTS CONDITIONED EXTERNAL INTERRUPTS TO VECTORED INTERRUPT CONTROLLER SYSTEM CLOCK CPU CLOCK ON CHIP PERIPHERAL CLOCKS AHB INTERFACE OSCILLATOR AND PLL INTERFACE VECTORED INTERRUPT CONTROLLER FIQ AND IRQ OUTPUTS CLOCK CONTROL BLOCK RESET CONTROL...

Page 123: ...gger interrupt outputs required by the VIC Generates remap outputs used by the memory map decoder Provides an identification register Supports external or watchdog reset status 9 2 RCPC Theory of Operation The RCPC allows users to control System Reset clocks power management and exter nal interrupt conditioning via an AMBA APB interface This control includes Enabling and disabling various clocks M...

Page 124: ...rates System Reset and RTC Reset outputs The RTC block is reset by the RTC reset output with the rest of the chip being reset by the System Reset The nRESETOUT output pin is driven by the System Reset The System Reset and RTC Reset are asserted by any of the following events An external reset a logic LOW signal on the external nRESETIN or nPOR input pins A signal from the internal Watchdog Timer A...

Page 125: ...ivided by 32768 to produce the 1 Hz RTC clock The UART clocks are generated from the 14 7456 MHz crystal oscillator To activate the RTC and UART clocks program the APBPeriphClkCtrl0 Register see Section 9 3 2 8 The SSP and LCD clocks are generated from the system clock frequency These clocks are dividable according to the values programmed in the SSPPrescaler and LCDPrescaler Registers To activate...

Page 126: ...e RCPC exits Sleep Mode and ensures an orderly transition to Active Mode An interrupt should be held active until the RCPC exits Sleep Mode NOTE Be sure there are no transmit or receive operations occurring when the LH75400 01 10 11 SoC device enters Standby Mode 9 2 3 4 Stop1 Mode Stop1 Mode stops all system clocks and disables the PLL but keeps the internal oscilla tors active The SoC enters thi...

Page 127: ...gister Identification 0x04 R 0x5400 ID Register Remap 0x08 RW 0x0 Remap Control Register SoftReset 0x0C RW 0x0000 Soft Reset Register ResetStatus 0x10 R 0x1 Reset Status Register ResetStatusClr 0x14 W Reset Status Clear Register SysClkPrescaler 0x18 RW 0xF System Clock Prescaler Register 0x1C 0x20 Reserved APBPeriphClkCtrl0 0x24 RW 0x3FF Peripheral Clock Control 0 Register APBPeriphClkCtrl1 0x28 R...

Page 128: ...2000 0x00 Table 9 4 Ctrl Register Definitions BITS FIELD NAME DESCRIPTION 31 10 Reserved Writing to these bits has no effect Reading returns 0 9 LOCK Lock 0 All RCPC registers accessible through the APB other thanthis bit and the IntClear Register see Section 9 3 2 14 are write protected 1 All RCPC APB accessible registers are write enabled default 8 Reserved Writing to these bits has no effect Re...

Page 129: ...LD PART_NUMBER RESET 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 RW R R R R R R R R R R R R R R R R ADDR 0xFFFE2000 0x04 Table 9 6 ID Register Definitions BITS FIELD NAME DESCRIPTION 31 16 Reserved Writing to these bits has no effect Reading returns 0 15 0 PART_NUMBER Part Number Digits Specifies the last four digits of the part number for example 5400 5401 5410 or 5411 Values for bits 4 and 0 vary from those...

Page 130: ...28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD SRVAL RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE2000 0x0C Table 9 10 SoftReset Register Definitions BITS FIELD NAME DESCRIPTION 31 16 Reserved Writing to these bits has no effe...

Page 131: ... Clear operation Table 9 11 ResetStatus Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD WDTO EXT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 RW R R R R R R R R R R R R R R R R ADDR 0xFFFE2000 0x10 Table 9 12 ResetStatus Register Definitions BITS FIELD NAME DESCRIPTI...

Page 132: ...ect on the RCPC NOTE The reset value of this register s bits is indeterminate Table 9 13 ResetStatusClr Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET RW W W W W W W W W W W W W W W W W BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD WDTO CLR EXT CLR RESET RW W W W W W W W W W W W W W W W W ADDR 0xFFFE2000 0x14 Table 9 14 ResetStatusClr Register Definitions BITS FIELD NAM...

Page 133: ...R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD HCLK RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 RW R R R R R R R R R R R R RW RW RW RW ADDR 0xFFFE2000 0x18 Table 9 16 SysClk Prescaler Register Definitions BITS FIELD NAME DESCRIPTION 31 4 Reserved Writing to these bits has no effect 3 0 HCLK HCLK Prescaler Prescale Count Shows the prescale count for the HCLK prescaler See Table 9 17 for valid values f...

Page 134: ... 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RTC U2 U1 U0 RESET 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 RW R R R R R R RW R R R R R R RW RW RW ADDR 0xFFFE2000 0x24 Table 9 19 APBPeriphClkCtrl0 Register Definitions BITS FIELD NAME DESCRIPTION 31 10 Reserved Writing to these bits has no effect Reading returns 0 9 RTC RTC Clock 0 Real time clock is runni...

Page 135: ... 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD SSP LCD RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RW R R R R R R RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE2000 0x28 Table 9 21 APBPeriphClkCtrl1 Register Definitions BITS FIELD NAME DESCRIPTION 31 16 Reserved Writing to these bits has no effect Reading re...

Page 136: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD DMA RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 RW R R R R R R R RW RW RW RW RW RW RW RW RW ADDR 0xFFFE2000 0x2C Table 9 23 AhbClkCtrl Register Definitions BITS FIELD NAME DESCRIPTION 31 9 Reserved Writing to these bits has no effe...

Page 137: ... 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD LCDPRESCALER RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R RW RW RW RW RW RW RW RW ADDR 0xFFFE2000 0x40 Table 9 25 LCDPrescaler Register Definitions BITS FIELD NAME DESCRIPTION 31 8 Reserved Writing to these bits has no effect Read...

Page 138: ... 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD SSPPRESCALER RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R RW RW RW RW RW RW RW RW ADDR 0xFFFE2000 0x44 Table 9 28 SSPPrescaler Register Definitions BITS FIELD NAME DESCRIPTION 31 8 Reserved Writing to these bits has no effect Read...

Page 139: ... RW RW RW RW RW RW ADDR 0xFFFE2000 0x80 Table 9 31 IntConfig Register Definitions BITS FIELD NAME DESCRIPTION 31 16 Reserved Writing to these bits has no effect Reading returns 0 15 14 Reserved Read as 0 do not modify 13 12 INT6 Configures External Interrupt INT6 00 Configures INT6 to be a LOW level trigger 01 Configures INT6 to be a HIGH level trigger 10 Configures INT6 to be a falling edge trigg...

Page 140: ... Configures External Interrupt INT1 00 Configures INT1 to be a LOW level trigger 01 Configures INT1 to be a HIGH level trigger 10 Configures INT1 to be a falling edge trigger 11 Configures INT1 to be a rising edge trigger 1 0 INT0 Configures External Interrupt INT0 00 Configures INT0 to be a LOW level trigger 01 Configures INT0 to be a HIGH level trigger 10 Configures INT0 to be a falling edge tri...

Page 141: ...er Definitions BITS FIELD NAME DESCRIPTION 31 7 Reserved Writing to these bits has no effect 6 INT6 Clear INT6 Interrupt 0 Does not clear the active edge triggered interrupt INT6 1 Clears the active edge triggered interrupt INT6 5 INT5 Clear INT5 Interrupt 0 Does not clear the active edge triggered interrupt INT5 1 Clears the active edge triggered interrupt INT5 4 INT4 Clear INT4 Interrupt 0 Does ...

Page 142: ...ble immediately out of reset 10 1 1 Interrupts The VIC accepts inputs from 32 interrupt source lines Seven of the interrupt source lines are external Twenty three of the interrupt source lines are internal Two interrupt source lines that can be used as software interrupts All 32 interrupt source lines can be enabled disabled and cleared individually and indi vidual status may be determined On rese...

Page 143: ...version specific for each device Table 10 1 Interrupt Assignments POSITION DESCRIPTION SOURCE 0 WDT Watchdog Timer 1 Not Used Can be used as a software interrupt 2 ARM7 DBGCOMMRX Sourced by the ARM7TDMI S Core 3 ARM7 DBGCOMMTX Sourced by the ARM7TDMI S Core 4 Timer0 Combined Timer0 5 Timer1 Combined Timer1 6 Timer2 Combined Timer2 7 External Interrupt 0 Sourced by the GPIO Block 8 External Interru...

Page 144: ...or Then enable that interrupt source as a vectored interrupt using the E field in that register Enable each interrupt line to be enabled whether vectored or default vectored using the IntEnable Register see Section 10 2 2 5 10 1 4 External Interrupts All external interrupts are conditioned by the RCPC module before being presented to the VIC External interrupt conditioning can be configured to one...

Page 145: ...l source For example the DMA Controller has a Clr Register that must be written with a value specific to the DMA Controller Other devices within the SoC have similar device specific ways of clear ing an interrupt generated by that device See the appropriate chapter in this Tech nical Data Sheet for information about clearing each device 2 The interrupt must be cleared within the VIC by writing any...

Page 146: ...without further processing 6 If the interrupt has been identified as an IRQ the active HIGH signal is routed for fur ther processing by interrupt vector and priority logic 7 The interrupt vector logic establishes whether the interrupt has been associated with a vectored interrupt If the signal is identified as a source calling for handling by a vec tored interrupt 0 15 the signal is routed to the ...

Page 147: ...t Vector Address into the VectAddr Register For default vectored interrupts the ISR determines the source of the interrupt and handles it appropriately 15 FIQ and IRQ interrupts are globally disabled by the CPU when an FIQ is asserted IRQ interrupts are globally disabled by the CPU when an IRQ is asserted The timing and circumstances of re enabling global interrupts and implementing interrupt nest...

Page 148: ...ufficient delay between the time when the source of the external interrupt is cleared and the time when the interrupt at the VIC is cleared This situation is due to the relatively slow risetime of the interrupt signal when being pulled to its inactive state by the pull up resistor The larger the resistor and load capacitance on the interrupt line the slower the rise time and the greater the delay ...

Page 149: ...0x114 RW 0x00000000 Vector Address 5 Register VectAdd 6 0x118 RW 0x00000000 Vector Address 6 Register VectAddr 7 0x11C RW 0x00000000 Vector Address 7 Register VectAddr 8 0x120 RW 0x00000000 Vector Address 8 Register VectAddr 9 0x124 RW 0x00000000 Vector Address 9 Register VectAddr 10 0x128 RW 0x00000000 Vector Address 10 Register VectAddr 11 0x12C RW 0x00000000 Vector Address 11 Register VectAddr ...

Page 150: ... Summary Cont d NAME ADDRESS OFFSET TYPE RESET VALUE DESCRIPTION Table 10 3 IRQStatus Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD IRQStatus RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD IRQStatus RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFFF000 0x000 Table 10 4 ...

Page 151: ... R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD FIQStatus RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFFF000 0x004 Table 10 6 FIQStatus Register Definitions BIT NAME DESCRIPTION 31 0 FIQStatus Interrupt Status After Masking Shows the status of the interrupts after masking by the IntEnable and IntSelect Registers 0 Interrupt is not ...

Page 152: ... 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RawInterrupt RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFFF000 0x008 Table 10 8 RawIntr Register Definitions BIT NAME DESCRIPTION 31 0 RawInterrupt Interrupt Status After Masking Shows the status of the interrupts be fore masking by the Enable Registers 0 A...

Page 153: ...FIELD IntSelect RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD IntSelect RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFFF000 0x00C Table 10 10 IntSelect Register Definitions BIT NAME DESCRIPTION 31 0 IntSelect Interrupt Type Selects the type of interrupt fo...

Page 154: ...W RW RW RW RW RW RW RW RW BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD IntEnable RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFFF000 0x010 Table 10 12 IntEnable Register Definitions BIT NAME DESCRIPTION 31 0 IntEnable Interrupt Enable Corresponds to the interrupt order in the Interrupt Assign ments table see Table 10 1 When any bit position i...

Page 155: ...e Clear RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW W W W W W W W W W W W W W W W W BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD IntEnable Clear RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW W W W W W W W W W W W W W W W W ADDR 0xFFFFF000 0x014 Table 10 14 IntEnClear Register Definitions BIT NAME DESCRIPTION 31 0 IntEnable Clear Clear IntEnable Bit Clears bits in the IntEnable Register 0 Has no effect ...

Page 156: ...RW RW RW RW RW RW RW RW RW RW BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD SoftInt RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFFF000 0x018 Table 10 16 SoftInt Register Definitions BIT NAME DESCRIPTION 31 0 SoftInt Generate Software Interrupt Setting a bit generates a software interrupt for the specific source interrupt before interrupt mask...

Page 157: ... 16 FIELD SoftInt Clear RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW W W W W W W W W W W W W W W W W BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD SoftInt Clear RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW W W W W W W W W W W W W W W W W ADDR 0xFFFFF000 0x01C Table 10 18 SoftIntClear BIT NAME DESCRIPTION 31 0 SoftInt Clear Clear SoftInt Register Bits Clears bits in the SoftInt Register 0 Has no effect 1...

Page 158: ...enerated at the end of the ISR When the VectAddr Register is written to To update the priority hardware Reading or writing to the register at other times can cause incorrect operation Table 10 19 VectAddr Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD VectorAddr RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW BIT 15 14 13 12 11 10 9 8 7 ...

Page 159: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD Default VectorAddr RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD Default VectorAddr RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFFF000 0x034 Table 10 22 DefVectAddr Register Definitions BIT NAME DESCR...

Page 160: ... 6 5 4 3 2 1 0 FIELD VICVectorAddr RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR VectAddr0 0xFFFFF000 0x100 VectAddr1 0xFFFFF000 0x104 VectAddr2 0xFFFFF000 0x108 VectAddr3 0xFFFFF000 0x10C VectAddr4 0xFFFFF000 0x110 VectAddr5 0xFFFFF000 0x114 VectAddr6 0xFFFFF000 0x118 VectAddr7 0xFFFFF000 0x11C VectAddr8 0xFFFFF000 0x120 VectAddr9 0xFFFFF000 0x124 V...

Page 161: ...8 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD E IntSource RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R RW RW RW RW RW RW ADDR VectCtrl0 0xFFFFF000 0x200 VectCtrl1 0xFFFFF000 0x204 VectCtrl2 0xFFFFF000 0x208 VectCtrl3 0xFFFFF000 0x20C VectCtrl4 0xFFFFF000 0x210 VectCtrl5 0xFFFFF000 0x214 VectCtr...

Page 162: ...EBI_MUX Register default to have the GPIO controlling the pin after a System Reset Bit 14 of the EBI_MUX Register can default to the data pins depending on the Boot Mode The alternative functions can then be accessed by pro gramming the IOCON registers The LCD_MUX does not allow individual control of the pins however it permits different LCD modes to be programmed Depending on the mode different p...

Page 163: ... Muxing Register PD_MUX 0x04 RW 0x0000 Pins PD6 INT6 to PD0 INT0 Muxing Register PE_MUX 0x08 RW 0x0000 Pins PE7 SSPRM to PE0 UARTRX2 Muxing Register TIMER_MUX 0x0C RW 0x0000 Timer Muxing Register LCD_MUX 0x10 RW 0x0000 LCD Mode Muxing Register PA_RES_MUX 0x14 RW 0xAAAA Pins PA7 D15 to PA0 D8 Resistor Muxing Register PB_RES_MUX 0x18 RW 0x0555 Pins PB5 nWAIT to PB0 nCS1 Resistor Muxing Register PC_R...

Page 164: ...alue is 0x4000 In 8 bit Mode the reset value is 0x0000 Table 11 2 EBI_MUX Register 16 bit Mode BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD DATA nWAIT nBLE1 nBLE0 nCE3 nCE2 nCE1 A23 A22 A21 A20 A19 A18 A17 A16 RESET 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R RW RW RW RW R...

Page 165: ...WAIT Source 0 PB5 1 nWAIT 12 nBLE1 PB4 nBLE1 Source 0 PB4 1 nBLE1 11 nBLE0 PB3 nBLE0 Source 0 PB3 1 nBLE0 10 nCE3 PB2 nCE3 Source 0 PB2 1 nCE3 9 nCE2 PB1 nCE2 Source 0 PB1 1 nCE2 8 nCE1 PB0 nCE1 Source 0 PB0 1 nCE1 7 A23 PC7 A23 Source 0 PC7 1 A23 6 A22 PC6 A22 Source 0 PC6 1 A22 5 A21 PC5 A21 Source 0 PC5 1 A21 4 A20 PC4 A20 Source 0 PC4 1 A20 3 A19 PC3 A19 Source 0 PC3 1 A19 2 A18 PC2 A18 Source...

Page 166: ... BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD INT6 INT5 INT4 INT3 INT2 INT1 INT0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x04 Table 11 6 PD_MUX Register Definitions BIT NAME DESCRIPTION 31 11 Reserved Writing to these bits has no effect Reading returns 0 10 9 INT6 Pin PD6 INT6 DREQ Source 00 PD6 01 INT6 10 DREQ 11 PD6 8 7 INT5 Pin PD5 ...

Page 167: ...MUX Register LH75401 and LH75400 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD SSPFRM SSPCLK SSPRX SSPTX CANTX CANRX UARTTX2 UARTRX2 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x08 Table 11 8 PE_MUX Register LH7...

Page 168: ...SSPCLK Source 0 PE6 1 SSPCLK 7 SSPRX PE5 SSPRX Source 0 PE5 1 SSPRX 6 SSPTX PE4 SSPTX Source 0 PE4 1 SSPTX 5 4 CANTX Pin PE3 CANTX UARTTX0 Source LH75401 and LH75400 SoC only 00 PE3 01 CANTX1 10 UARTTX0 11 PE3 3 2 CANRX Pin PE2 CANRX UARTRX0 Source LH75401 and LH75400 SoC only 00 PE2 01 CANRX1 10 UARTRX0 11 PE2 5 2 Reserved Always write 0 LH75410 and LH75411 SoC only 1 UARTTX2 PE1 UARTTX2 Source 0...

Page 169: ...0 FIELD CTCAP2B CTCAP2A CTCAP1B CTCAP1A CTCAP0E CTCAP0D CTCAP0C CTCAP0B CTCAP0A CTCLK RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x0C Table 11 11 TIMER_MUX Register Definitions BITS NAME DESCRIPTION 31 16 Reserved Writing to these bits has no effect Reading returns 0 15 14 CTCAP2B Pin PF6 CTCAP2B CTCMP2B Source 00 PF6 01 CTCAP2B 10 CTCM...

Page 170: ...0D 5 CTCAP0C PF0 CTCAP0C Source 0 PF0 1 CTCAP0C 4 3 CTCAP0B Pin PG7 CTCAP1B CTCMP0B Source 00 PG7 01 CTCAP0B 10 CTCMP0B 11 PG7 2 1 CTCAP0A Pin PG6 CTCAP0A CTCMP0A Source 00 PG6 01 CTCAP0A 10 CTCMP0A 11 PG6 0 CTCLK PG5 CTCLK Source 0 PG5 1 CTCLK Table 11 11 TIMER_MUX Register Definitions Cont d BITS NAME DESCRIPTION ...

Page 171: ... MODE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R RW RW RW ADDR 0xFFFE5000 0x10 Table 11 13 LCD_MUX Register Definitions LH75401 and LH75411 SoC Devices BIT NAME DESCRIPTION 31 3 Reserved Writing to these bits has no effect Reading returns 0 2 0 MODE LCD Mode 000 No LCD 001 4 bit Mono STN Mode 010 4 bit Mono STN Dual Mode 011 8 bit Mono Color STN Mode 100 TFT Mode 101 throug...

Page 172: ... 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x14 Table 11 16 PA_RES_MUX Register Definitions BITS NAME DESCRIPTION 31 16 Reserved Writing to these bits has no effect Reading returns 0 15 14 PA7 Pin PA7 D15 Resistor Source 00 Pull down 01 Pull up 10 No pull up or pull down default 11 Pull up 13 12 PA6 Pin PA6 D14 Resistor Source 00 Pull down 01 ...

Page 173: ... up 10 No pull up or pull down default 11 Pull up 3 2 PA1 Pin PA1 D9 Resistor Source 00 Pull down 01 Pull up 10 No pull up or pull down default 11 Pull up 1 0 PA0 Pin PA0 D8 Resistor Source 00 Pull down 01 Pull up 10 No pull up or pull down default 11 Pull up Table 11 16 PA_RES_MUX Register Definitions Cont d BITS NAME DESCRIPTION ...

Page 174: ...RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x18 Table 11 18 PB_RES_MUX Register Definitions BITS NAME DESCRIPTION 31 12 Reserved Writing to these bits has no effect 11 10 PB5 Pin PB5 nWAIT Resistor Source 00 Pull down 01 Pull up default 10 No pull up or pull down 11 Pull up 9 8 PB4 Pin PB4 nBLE1 Resistor Source 00 Pull down 01 Pull up default 10 No pull up or pull down 11 Pull up 7 6 PB3 Pin...

Page 175: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x1C Table 11 20 PC_RES_MUX Register Definitions BITS NAME DESCRIPTION 31 16 Reserved Writing to these bits has no effect Reading returns 0 15 14 PC7 Pin PC7 A23 Resistor Source 00 Pull down default 01 Pull up 10 No pull up or pull down 11 Pull down 13 12 PC6 Pin PC6 A22 Resistor Source 00 Pull down defau...

Page 176: ...Pull up 10 No pull up or pull down 11 Pull down 3 2 PC1 Pin PC1 A17 Resistor Source 00 Pull down default 01 Pull up 10 No pull up or pull down 11 Pull down 1 0 PC0 Pin PC0 A16 Resistor Source 00 Pull down default 01 Pull up 10 No pull up or pull down 11 Pull down Table 11 20 PC_RES_MUX Register Definitions Cont d BITS NAME DESCRIPTION ...

Page 177: ... 1 0 1 0 RW R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x20 Table 11 22 PD_RES_MUX Register Definitions BITS NAME DESCRIPTION 31 14 Reserved Writing to these bits has no effect Reading returns 0 13 12 PD6 Pin PD6 INT6 DREQ Resistor Source 00 Pull down default 01 Pull up 10 No pull up or pull down 11 Pull down 11 10 PD5 Pin PD5 INT5 DACK Resistor Source 00 Pull down 01 Pull up 10...

Page 178: ...Resistor Source 00 Pull down 01 Pull up 10 No pull up or pull down default 11 No pull up or pull down 1 0 PD0 Pin PD0 INT0 Resistor Source 00 Pull down 01 Pull up 10 No pull up or pull down default 11 No pull up or pull down Table 11 22 PD_RES_MUX Register Definitions Cont d BITS NAME DESCRIPTION ...

Page 179: ...o the Pin PE2 UARTRX0 Resistor Source Table 11 23 PERES_MUX Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 RESET 0 1 9 0 0 1 9 0 0 1 0 1 0 1 0 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x24 Table 11 2...

Page 180: ... default 10 No pull up or pull down 11 Pull up 5 4 PE2 Pin PE2 CANRX UARTRX0 Resistor Source LH75400 and LH75401 SoC Pin PE2 UARTRX0 Resistor Source LH75410 and LH75411 SoC 00 Pull down 01 Pull up default 10 No pull up or pull down 11 Pull up 3 2 PE1 Pin PE1 UARTTX2 Resistor Source 00 Pull down 01 Pull up default 10 No pull up or pull down 11 Pull up 1 0 PE0 Pin PE0 UARTRX2 Resistor Source 00 Pull...

Page 181: ... R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R RW RW RW RW RW RW RW RW ADDR 0xFFFE5000 0x28 Table 11 26 ADC_MUX Register BIT NAME DESCRIPTION 31 8 Reserved Writing to these bits has no effect Reading returns 0 7 PJ7 Pin AN3 PJ7 Source 0 AN3 LR Y 1 PJ7 6 PJ6 Pin AN4 PJ6 Source 0 ...

Page 182: ...egisters by the ARM and an AHB port for data transfers 12 1 DMA Controller Features The DMA Controller has the following features Four data streams Three modes of transfer Memory to Memory selectable on Stream3 only Peripheral to Memory all streams Memory to Peripheral all streams Built in data stream arbiter Seven registers for each stream DMA enable Transfer Size Byte Half word Word Burst Size 1...

Page 183: ...f the four data streams has its own independent set of DMA Registers and address transfer count counters In addition Stream2 provides a set of external signals for initiating and controlling DMA transfers between external peripherals and memory These signals DREQ and DACK are brought out to external pins that are multiplexed with other functions Stream3 can carry out memory to memory DMA transfers...

Page 184: ...memory transfer the transfer starts immediately without the DMA waiting for the external request signal in step 1 The software workaround to this is Set up a memory to memory access Let the memory to memory complete Set up the peripheral to memory transfer but without the enable bit set Perform a second write operation with the enable bit set When the DMA is configured to perform an external memor...

Page 185: ...ared independently Each stream also has its own error flag An error flag is set when the data stream transfer is aborted due to an ERROR response from an AHB slave Each of the four error flags can be separately masked and cleared The masked interrupt and error flags are all combined into a single interrupt output 12 2 2 DMA Controller Timing Diagrams Figure 12 1 and Figure 12 2 show examples of DM...

Page 186: ...ry User s Guide Direct Memory Access Controller 7 15 03 12 5 Figure 12 1 Peripheral to Memory Data Transfer Timing Pa0 DREQ DACK A 23 0 D 15 0 nCS0 nWE nCS1 Pa1 Pa2 Pa3 Pd0 Pd1 Pd2 Pd3 Ma0 Ma1 Ma2 Ma3 Md0 Md1 Md2 Md3 LH754xx 10 ...

Page 187: ...oller LH75400 01 10 11 Preliminary User s Guide 12 6 7 15 03 Figure 12 2 Memory to Peripheral Data Transfer Timing Ma0 DREQ DACK A 23 0 D 15 0 nCS0 nWE nCS1 Ma1 Ma2 Ma3 Md0 Md1 Md2 Md3 Pa0 Pa1 Pa2 Pa3 Pd0 Pd1 Pd2 Pd3 LH754xx 11 ...

Page 188: ...tream1 0x040 R W Data Stream1 Register Base Stream2 0x080 RW Data Stream2 Register Base Stream3 0x0C0 RW Data Stream3 Register Base Mask 0x0F0 RW DMA Interrupt Mask Register Clr 0x0F4 W DMA Interrupt Clear Status 0x0F8 R DMA Status Register Table 12 3 Data Stream Register Summary NAME ADDRESS OFFSET TYPE DESCRIPTION SourceLo 0x000 RW Source base address lower 16 bits SourceHi 0x004 RW Source base ...

Page 189: ...sfer When the DMA Controller is enabled the content of the Destination Base Address Register is loaded in the Current Destination Address Register 12 3 2 3 Maximum Count Register This register is programmed with the maximum data unit count of the next DMA transfer The data unit is equal to the source to DMA data width byte half word or word When the DMA Controller is enabled the content of the Max...

Page 190: ... as possible until MaxCnt expires 10 Reads as zero Always write 0 to this bit 9 AddrMode Current Source Destination Loading Determines whether the Current Source Ad dress Register and the Current Destination Address Register load from the Source Base registers and the Destination Base registers respectively when the DMA con troller is enabled 0 Wrapping Address Mode for source and destination Regi...

Page 191: ...anged holding the same value during the entire DMA transfer 1 Current Source Register increments as data transfers from a source to the DMA The value increments by the HSIZE value at the end of the address phase of the AHB transfer 0 Enable DMA Controller Enable Disable Enables or disables the DMA Controller The Source Base Destination Base and Maximum Count Registers must be set before the DMA is...

Page 192: ...y registers that hold the current value of the destination address pointer The value in the registers is used as an AHB address in a DMA to destination data transfer over the AHB If the DeInc bit in the Control Register is set to 1 the value in the Current Destination Reg isters increments as data transfers from the DMA to a destination The value increments at the end of the address phase of the A...

Page 193: ... BIT NAME FUNCTION 31 8 Reserved Read as zero Do not write 7 MaskE3 Data Stream3 Error Interrupt 0 Disables data stream3 error interrupt 1 Enables data stream3 error interrupt 6 MaskE2 Data Stream2 Error Interrupt 0 Disables data stream2 error interrupt 1 Enables data stream2 error interrupt 5 MaskE1 Data Stream1 Error Interrupt 0 Disables data stream1 error interrupt 1 Enables data stream1 error ...

Page 194: ... flag in the Status Register 6 ClearE2 Clear Do Not Clear ErrorInt2 Flag 0 Does not clear the ErrorInt2 flag in the Status Register 1 Clears the ErrorInt2 flag in the Status Register 5 ClearE1 Clear Do Not Clear ErrorInt1 Flag 0 Does not clear the ErrorInt1 flag in the Status Register 1 Clears the ErrorInt1 flag in the Status Register 4 ClearE0 Clear Do Not Clear ErrorInt0 Flag 0 Does not clear th...

Page 195: ...ot active 1 Data stream3 is active 10 Active2 Data Stream2 Active Inactive 0 Data stream2 is not active 1 Data stream2 is active 9 Active1 Data Stream1 Active Inactive 0 Data stream1 is not active 1 Data stream1 is active 8 Active0 Data Stream0 Active Inactive 0 Data stream0 is not active 1 Data stream0 is active 7 ErrorInt3 Data Stream3 Error Interrupt Flag Specifies the data stream3 error interr...

Page 196: ...esponding to data stream0 through data stream3 An error interrupt flag is set when its corresponding data stream s transfer is aborted due to an AHB transfer error When this occurs the stream is disabled until the Enable bit is again set by software The Active flags are used to indicate if a data stream is transferring data It is HIGH if a data transfer is in progress The Active flags have the sam...

Page 197: ...Os Each FIFO is 16 words deep by 32 bits wide In Single Panel STN Mode the LCD DMA FIFOs are made to appear as a single FIFO of twice the size The buffered pixel coded data is then unpacked via a pixel serializer In 12 bit per pixel Mode the CLCDC uses the unpacked data directly to generate the pixel value In all other bit per pixel modes the CLCDC uses the unpacked data to index its pal ette RAM ...

Page 198: ...NTERFACE PANEL CLOCK GENERATOR TIMING CONTROLLER CONTROL AND STATUS REGISTER UPPER PANEL FORMATTER UPPER PANEL OUTPUT FIFO STN TFT DATA SELECT UPPER STN DATA LCD PANEL CLOCK LCD PANEL CONTROL INPUT FIFO CONTROL PIXEL SERIALIZER PALETTE 128 32 GRAY SCALER CLCDCLK UPPER PANEL DMA FIFO LOWER PANEL DMA FIFO LOWER PANEL FORMATTER INTERRUPT GENERATION INTERRUPTS LOWER PANEL OUTPUT FIFO LOWER STN DATA TF...

Page 199: ...if LCDC is not needed Supported Data Format Little Endian Additional Features Programmable timing for different display panels 256 entry 16 bit palette RAM physically arranged as a 128 32 bit RAM AC bias signal for STN panels and a data enable signal for TFT panel Programmable Parameters Horizontal Horizontal Front Porch HFP Horizontal Back Porch HBP Horizontal Synchronization Pulse Width HSW Numb...

Page 200: ...ot be placed in TCM SRAM 13 2 1 LCD DMA FIFOs The CLCDC has an upper LCD DMA FIFO and a lower LCD DMA FIFO These FIFOs can be independently controlled to cover single and dual panel LCDs Each FIFO is 16 words deep by 32 bits wide In single panel modes the LCD DMA FIFOs are made to appear as a single FIFO of twice the size The water level marks within each FIFO are set so that each FIFO requests da...

Page 201: ... p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 p23 p24 p25 p26 p27 p28 p29 p30 p31 Table 13 2 Frame Buffer Pixel Storage Format 31 16 bpp DMA FIFO OUTPUT BITS 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16 2 p15 p14 p13 p12 p11 p10 p9 p8 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 4 p7 p6 p5 p4 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 8 p3 p2 ...

Page 202: ...ort of the dual port palette RAM is used as a Read Only port and is connected to the unpacker and grayscaler Table 13 4 shows the bit representations of each word in the palette for TFT and STN displays NOTE Blue and red palette data can swap places depending on the setting of bit 8 of the LCD Control Register see Section 13 3 2 8 Table 13 4 Palette Data Storage BIT TFT BIT STN NAME DESCRIPTION 31...

Page 203: ...lower panel formatters each comprise three 3 bit red green and blue shift left registers When enough data is available a byte is constructed by multiplexing the registered data to the correct bit position to satisfy the LCD panel s RGB data pattern The byte transfers to the 3 byte FIFO which has sufficient space to store eight color pixels The CLCDC has four individually maskable interrupt conditi...

Page 204: ...T UP TO 16 BIT BUS 1 Palletized 2 colors selected from 65 536 available colors 2 Palletized 4 colors selected from 65 536 available colors 4 Palletized 16 colors selected from 65 536 available colors 8 Palletized 256 colors selected from 65 536 available colors 12 Direct 4 4 4 RGB Table 13 6 Supported Color STN LCD Panels bpp SOURCE COLOR STN SINGLE AND DUAL PANEL 8 BIT BUS 1 Palletized 2 colors s...

Page 205: ... 1 Duty cycle is determined by pixels on pixels on pixels off 2 Resulting intensity 000 black 100 white Table 13 8 Color STN Intensities From Gray Scale Modulation 4 BIT PALETTE VALUE DUTY CYCLE1 RESULTING INTENSITY2 0b0000 0 90 00 0 0b0001 10 90 11 1 0b0010 18 90 20 0 0b0011 24 90 26 7 0b0100 30 90 33 3 0b0101 36 90 40 0 0b0110 40 90 44 4 0b0111 45 90 50 0 0b1000 45 90 50 0 0b1001 50 90 55 6 0b10...

Page 206: ...Register Timing2 0x008 RW 0x0000000 Clock and Signal Polarity Control Register 0x00C RW Reserved UPBASE 0x010 RW 0x0000000 Upper Panel Frame Buffer Base Address Register LPBASE 0x014 RW 0x00000000 Lower Panel Frame Buffer Base Address Register INTRENABLE 0x018 RW 0x00000000 Interrupt Enable Register Ctrl 0x01C RW 0x0000 LCD Panel Parameters LCD Panel Power and CLCDC Control Register Status 0x020 R...

Page 207: ... the previous line has been de assert ed the value in HBP counts the number of pixel clocks to wait before starting the next display line HBP can generate a delay of 1 to 256 pixel clock cycles 23 16 HFP Horizontal Front Porch Specifies the number of LCDDCLK periods between the end of active data and the rising edge of LCDLP that is the number of pixel clock intervals at the end of each line or ro...

Page 208: ...data path latency forces some restrictions on the usable minimum values for horizontal porch width in STN Mode The minimum values are HSW 2 and HBP 2 Single Panel Mode HSW 3 HBP 5 HFP 5 Panel Clock Divisor PCD 1 CLCDCLK 3 Dual Panel Mode HSW 3 HBP 5 HFP 5 PCD 5 CLCDCLK 7 If sufficient time is given at the start of the line for example setting HSW 6 HBP 10 data will not get corrupted for PCD 4 mini...

Page 209: ...orch Specifies the number of inactive lines at the end of the frame before the vertical synchronization period that is the number of line clocks to insert at the end of each frame Program to zero on passive displays otherwise reduced contrast will result Once a complete frame of pixels is transmitted to the LCD display the value in VFP counts the number of line clock periods to wait After the coun...

Page 210: ...state 0 LCDEN output pin is active HIGH in TFT Mode 1 LCDEN output pin is active LOW in TFT Mode 13 IPC Invert Panel Clock Selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines 0 Data is driven on the LCDs data lines on the rising edge of LCDDCLK 1 Data is driven on the LCDs data lines on the falling edge of LCDDCLK 12 HIS Invert Horizontal Synchronization I...

Page 211: ...D vertical synchronization This event causes the LNBU bit and an optional interrupt to be generated The LNBU bit indicates that it is safe to update both the UPBASE and LPBASE Registers The interrupt can be used to reprogram the base address when generating double buffered video Table 13 16 UPBASE Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD LCDUPBASE RESET 0 0 0 0 0 0 0 0 0 ...

Page 212: ...ization This event causes the LNBU bit and an optional interrupt to be generated The LNBU bit indicates that it is safe to update both the UPBASE and LPBASE Registers The interrupt can be used to reprogram the base address when generating double buffered video Table 13 18 LPBASE Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD LCDLPBASE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW...

Page 213: ... RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R RW RW RW RW R ADDR 0xFFFF4000 0x18 Table 13 21 INTRENABLE Register Definitions BIT NAME DESCRIPTION 31 5 Reserved Writing to these bits has no effect Reading returns 0 4 MBERRINTRENB AHB Master Error Interrupt Enable 1 Enables the AHB Master Error Interrupt to be passed to the Raw Interrupt Status Register 3 VCOMPINTRENB Vertical Comp...

Page 214: ...e bits has no effect Reading returns 0 16 WATERMARK LCD DMA FIFO Watermark Level 0 HBUSREQM is raised when either of the two LCD DMA FIFOs have four or more empty locations 1 HBUSREQM is raised when either of the LCD DMA FIFOs have eight or more empty locations 15 LDmaFIFOTME LCD DMA FIFO Test Mode Enable 0 LCD DMA FIFO inaccessible to user 1 LCD DMA FIFO Read Write access for FIFO RAM testing Set...

Page 215: ...cleared and bit 7 is set unexpected results occur 3 1 LcdBpp LCD Bits per Pixel 000 1 bpp 001 2 bpp 010 4 bpp 011 8 bpp 100 12 bpp 16 bits fetched from memory 101 Reserved 110 Reserved 111 Reserved 0 LcdEn LCD Controller Enable 0 LCD Controller is disabled 1 LCD Controller is enabled LCD displays require the LCD to be running before power is applied For this rea son the LCD s power on control bit ...

Page 216: ...an ERROR response is received by the master interface during a transaction with a slave When an ERROR response is encountered the master interface enters an error state until it receives a signal that the error has been cleared 3 VCOMP Vertical Compare Interrupt Asserted when one of four vertical display regions selected via 13 12 of the LCD Control Register is reached see Section 13 3 2 8 The int...

Page 217: ... Table 13 26 Interrupt Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD MBERRINTRENB VCOMPINTRENB LNBUINTRENB FUFINTRENB RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFF4000 0x24 Table 13 27 Interrupt Register Definitions BIT...

Page 218: ...4 3 2 1 0 FIELD LCDUPCURR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFF4000 0x28 Table 13 29 UPCURR Register Definitions BIT NAME DESCRIPTION 31 0 LCDUPCURR Current Upper Panel Data DMA Address Contains the approximate current upper panel data DMA address Table 13 30 LPCURR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD LCDLPCURR RESET 0 0...

Page 219: ...it For TFT displays bits 3 0 of the palettes are used For color STN displays bits 4 1 of the red blue and green palettes are used For monochrome STN displays only the red palette bits 4 1 are used Note that the palettes are accessed 32 bits at a time NOTE Blue and red palette data can swap places depending on the setting of bit 8 of the LCD Control Register see Section 13 3 2 8 Table 13 32 Palette...

Page 220: ...plied with the standard TFT output from the LCD Controller and produce the necessary control and data signals to interface to an HR TFT type display 13 4 1 HRTFTC Operating Modes The HRTFTC has two operating modes Bypass Mode or HR TFT Mode The Setup Reg ister setting specifies the operating mode of the HRTFTC see Section 13 4 5 1 13 4 1 1 Bypass Mode Bypass Mode is the default mode after a System...

Page 221: ...g HR TFT Mode program the Setup Register first followed by Timing registers 1 and 2 After these registers are programmed the LCD Controller can be enabled and the Control Register can be used The HRTFTC generates the MOD signal automatically By default activation of MOD occurs 2 SPS rising edge clocks after activation of the controller This can be repro grammed for a longer or shorter wait or can ...

Page 222: ...egister BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD PPL CR RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 RW R R R RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE4000 0x000 Table 13 36 Setup Register Definitions BITS NAME FUNCTION 31 13 Reserved Writing to these bits has...

Page 223: ...1 10 Reserved Writing to these bits has no effect Reading returns 0 9 MODOVRD MOD Signal Override Enable Puts the value of MODVAL directly onto the MOD signal 0 LCDMOD pin goes HIGH after the SPS periods specified by the MODDEL field of the TIMING1 Register 1 LCDMOD pin equals the state of MODVAL bit in this register 8 MODVAL Mod Signal Value Specifies the value to force onto the MOD signal 7 5 Re...

Page 224: ...ting to these bits has no effect Reading returns 0 13 12 MODDEL LCDMOD LOW Delay Controls the delay number of LCDSPS rising edges to hold LCDMOD LOW before transitioning HIGH Program with value required 1 Range from 1 to 4 11 8 PSDEL CLSDEL CLCD to LCDPS Delay Controls the delay number of LCDDCLK periods from the first detected LOW in horizontal sync from the CLCD to the falling edge of LCDPS and ...

Page 225: ... RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE4000 0x00C Table 13 42 Timing2 Register Definitions BITS NAME FUNCTION 31 16 Reserved Writing to these bits has no effect Reading returns 0 15 9 SPLVALUE SPL Pulse Delay Delays SPL pulse during vertical front and back porches The delay must be programmed to a value greater than HSW HBP see the CLCD...

Page 226: ... 2 shows that the duration of the LCDLP signal is controlled by Timing0 HSW the HSW bit field in the Timing0 Register Figure 13 2 also shows that the polarity of the LCDLP signal is set by Timing2 IHS 13 5 2 STN Vertical Timing Figure 13 3 shows typical vertical timing waveforms for STN panels 13 5 3 TFT Horizontal Timing Figure 13 4 shows typical horizontal timing waveforms for TFT panels 13 5 4 ...

Page 227: ... 8 BIT COLOR OR MONO NOTES 1 The CLCDC clock from the RCPC is scaled within the CLCDC and used to produce the LCDDCLK output CLCDC registers set timing in terms of LCDDCLK pulses to produce the other signals that control an STN display 2 The duration ot the LCDLP signal is controlled by Timing0 HSW the HSW bit field in the Timing0 Register 3 The polarity of the LCDLP signal is set by Timing2 IHS T...

Page 228: ...RIZONTAL LINES SEE TFT HORIZONTAL TIMING DIAGRAM ENUMERATED IN HORIZONTAL LINES FRONT PORCH ALL LINES FOR ONE FRAME VSS LCDVDDEN DIGITAL SUPPLY ENABLE FOR HIGH VOLTAGE SUPPLIES LCDDCLK PANEL CLOCK Timing2 PCD Timing2 BCD Timing2 IPC LCDEN DATA ENABLE Timing2 ACB Timing2 IOE LCDFP VERTICAL SYNCHRONIZATION PULSE Timing1 IVS PIXEL DATA AND HORIZONTAL CONTROL SIGNALS FOR ONE FRAME NOTES 1 Signal polar...

Page 229: ...ng0 HBP Timing0 PPL D001 D002 D ONE LINE OF LCD DATA DNNN Timing0 HFP HORIZONTAL BACK PORCH HORIZONTAL FRONT PORCH ENUMERATED IN LCDDCLKS ENUMERATED IN LCDDCLKS LH754xx 79 LCDDCLK IS SUPPRESSED DURING LCDLP NOTES 1 The CLCDC clock from the RCPC is scaled within the CLCDC and used to produce the LCDDCLK output CLCDC registers set timing in terms of LCDDCLK pulses to produce the other signals that c...

Page 230: ...INES SEE TFT HORIZONTAL TIMING DIAGRAM ENUMERATED IN HORIZONTAL LINES FRONT PORCH ALL LINES FOR ONE FRAME VSS LCDVDDEN DIGITAL SUPPLY ENABLE LCDDCLK PANEL CLOCK Timing2 PCD Timing2 BCD Timing2 IPC LCDEN DATA ENABLE Timing2 ACB Timing2 IOE LCDFP VERTICAL SYNCHRONIZATION PULSE Timing1 IVS PIXEL DATA AND HORIZONTAL CONTROL SIGNALS FOR ONE FRAME NOTES 1 Signal polarties may vary for some displays 2 Th...

Page 231: ...cale LCDPS SHOWN FOR REFERENCE LCDLP HORIZONTAL SYNCHRONIZATION PULSE INPUTS TO THE HRTFTC FROM THE CLCDC OUTPUTS FROM THE HRTFTC TO THE PANEL LCDDCLK PANEL CLOCK Timing2 PCD Timing2 BCD Timing2 IPC Timing2 CPL LCDVD 11 0 LCDDCLK DELAYED FOR HR TFT LCDVD 11 0 DELAYED FOR HR TFT LCDSPL HR TFT START PULSE LEFT LCDLP HORIZONTAL SYNCHRONIZATION PULSE LCDCLS LCDPS LCDREV LCDEN DATA ENABLE LH754xx 80 NO...

Page 232: ... program mable 32 bit wide DMA FIFOs Each FIFO is 16 words deep by 32 bits wide In single panel STN Mode the LCD DMA FIFOs are made to appear as a single FIFO of twice the size The buffered pixel coded data is then unpacked via a pixel serializer Depending on the LCD type and mode the unpacked data can represent either an actual true display value or an address to a 256 16 bit wide palette RAM val...

Page 233: ...CE PANEL CLOCK GENERATOR TIMING CONTROLLER CONTROL AND STATUS REGISTER UPPER PANEL FORMATTER UPPER PANEL OUTPUT FIFO STN TFT DATA SELECT UPPER STN DATA LCD PANEL CLOCK LCD PANEL CONTROL INPUT FIFO CONTROL PIXEL SERIALIZER PALETTE 128 32 GRAY SCALER CLCDCLK UPPER PANEL DMA FIFO LOWER PANEL DMA FIFO LOWER PANEL FORMATTER INTERRUPT GENERATION INTERRUPTS LOWER PANEL OUTPUT FIFO LOWER STN DATA TFT DATA...

Page 234: ...Vertical Vertical Front Porch VFP Vertical Back Porch VBP Vertical Synchronization Pulse Width VSW Number of Lines per Panel LPP Panel related Parameters Display type STN mono Bits per pixel STN 4 bit Interface Mode STN Single Panel Mode AC panel bias Panel clock frequency Number of panel clocks per line Signal polarity active HIGH or LOW Little Endian data format Interrupt generation event 14 2 L...

Page 235: ...ata depending on the operating mode In Dual Panel Mode data is alternately read from the upper and lower LCD DMA FIFOs Depending on the operating mode the extracted data is used to point to a grayscale value in the palette RAM or is directly applied to a LCD panel input 14 2 3 How Pixels are Stored in Memory Table 14 1 and Table 14 2 show the data structure in each DMA FIFO word corresponding to t...

Page 236: ...alette 14 2 5 Grayscale Algorithm A patented grayscale algorithm drives monochrome STN panels providing 15 grayscales The grayscaler transforms each 4 bit gray value into a sequence of activity per pixel over several frames relying somewhat on the display characteristics to give the representation of grayscales See Table 14 4 Data bit values from the grayscaler are shifted into the register in the...

Page 237: ... grayscales 2 Greater than four bpp can be programmed however using these modes does not make sense since the maximum number of grayscales supported on this display is 15 Table 14 4 STN Intensities From Grayscale Modulation 4 BIT PALETTE VALUE DUTY CYCLE1 RESULTING INTENSITY2 0b0000 0 90 00 0 0b0001 10 90 11 1 0b0010 18 90 20 0 0b0011 24 90 26 7 0b0100 30 90 33 3 0b0101 36 90 40 0 0b0110 40 90 44 ...

Page 238: ... Register Timing2 0x008 RW 0x0000000 Clock and Signal Polarity Control Register 0x00C RW Reserved UPBASE 0x010 RW 0x0000000 Upper Panel Frame Buffer Base Address Register LPBASE 0x014 RW 0x00000000 Lower Panel Frame Buffer Base Address Register INTRENABLE 0x018 RW 0x00000000 Interrupt Enable Register CTRL 0x01C RW 0x0000 LCD Panel Parameters LCD Panel Power and LCDC Control Register Status 0x020 R...

Page 239: ...the previous line has been de asserted the value in HBP counts the number of pixel clocks to wait before starting the next display line HBP can generate a delay of 1 to 256 pixel clock cycles 23 16 HFP Horizontal Front Porch Specifies the number of LCDDCLK periods between the end of active data and the rising edge of LCDLP that is the number of pixel clock intervals at the end of each line or row ...

Page 240: ... to propagate down the FIFO path in the LCD interface The data path latency forces some restrictions on the usable minimum values for horizontal porch width in STN Mode The minimum values are HSW 2 and HBP 2 Single Panel Mode HSW 3 HBP 5 HFP 5 Panel Clock Divisor PCD 1 LCDCLK 3 Dual Panel Mode HSW 3 HBP 5 HFP 5 PCD 5 LCDCLK 7 If sufficient time is given at the start of the line for example setting...

Page 241: ...ch Specifies the number of inactive lines at the end of frame before ver tical synchronization period that is the number of line clocks to insert at the end of each frame Program to zero on passive displays otherwise reduced contrast will result Once a complete frame of pixels is transmitted to the LCD display the value in VFP counts the num ber of line clock periods to wait After the count has el...

Page 242: ...data is available In Active Display Mode data is driven onto the LCD data lines at the pro grammed edge of LCDDCLK when LCDEN is in its active state 0 LCDEN output pin is active HIGH 1 LCDEN output pin is active LOW 13 IPC Invert Panel Clock Selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines 0 Data is driven on the LCDs data lines on the rising edge of LC...

Page 243: ...nchronization This event causes the LNBU bit and an optional interrupt to be generated The LNBU bit indicates that it is safe to update both the UPBASE and LPBASE Registers The interrupt can be used to reprogram the base address when generating double buffered video Table 14 13 UPBASE Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD LCDUPBASE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 244: ... This event causes the LNBU bit and an optional interrupt to be generated The LNBU bit indicates that it is safe to update both the UPBASE and LPBASE Registers The interrupt can be used to reprogram the base address when generating double buffered video Table 14 15 LPBASE Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD LCDLPBASE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW ...

Page 245: ...R R R R R R R R R R R RW RW RW RW R ADDR 0xFFFF4000 0x18 Table 14 18 INTRENABLE Register Definitions BIT NAME DESCRIPTION 31 5 Reserved Writing to these bits has no effect Reading returns 0 4 MBERRINTRENB AHB Master Error Interrupt Enable 1 Enables the AHB Master Error Interrupt to be passed to the Raw Interrupt Status Register 3 VCOMPINTRENB Vertical Compare Interrupt Enable 1 Enables the Vector ...

Page 246: ...these bits has no effect Reading returns 0 16 WATERMARK LCD DMA FIFO Watermark Level 0 HBUSREQM is raised when either of the two LCD DMA FIFOs have four or more empty locations 1 HBUSREQM is raised when either of the LCD DMA FIFOs have eight or more empty locations 15 LDmaFIFOTME LCD DMA FIFO Test Mode Enable 0 LCD DMA FIFO inaccessible to user 1 LCD DMA FIFO Read Write access for FIFO RAM testing...

Page 247: ...Bits per Pixel 000 1 bpp 001 2 bpp 010 4 bpp 011 8 bpp 100 12 bpp 16 bits fetched from memory 101 Reserved 110 Reserved 111 Reserved 0 LcdEn LCD Controller Enable 0 LCD Controller is disabled 1 LCD Controller is enabled LCD displays require that the LCD is running before power is applied For this reason the LCD s power on control bit 11 is not set to 1 un less both LcdEn and LcdPwr are set to 1 Mo...

Page 248: ... response is re ceived by the master interface during a transaction with a slave When such an error is encountered the master interface enters an error state and re mains in this state until clearance of the error has been signaled to it 3 VCOMP Vertical Compare Interrupt Asserted when one of four vertical display re gions selected via the LCD Control Register with bits 13 12 is reached The interr...

Page 249: ... 14 23 Interrupt Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD MBERRINTRENB VCOMPINTRENB LNBUINTRENB FUFINTRENB RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFF4000 0x24 Table 14 24 Interrupt Register Definitions BIT NAME ...

Page 250: ... 2 1 0 FIELD LCDUPCURR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFF4000 0x28 Table 14 26 UPCURR Register Definitions BIT NAME DESCRIPTION 31 0 LCDUPCURR Current Upper Panel Data DMA Address Contains the approximate current upper panel data DMA address Table 14 27 LPCURR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD LCDLPCURR RESET 0 0 0 ...

Page 251: ... for a color display Note that the palettes are accessed 32 bits at a time 14 3 3 LCDC Interrupts The single combined interrupt CLCDINTR drives the VIC If any of the four interrupt con ditions occurs this signal is asserted Each of the four individual maskable interrupt conditions is enabled or disabled by chang ing the mask bits in the INTRENABLE Register Provision of individual outputs along wit...

Page 252: ...erflow interrupt when the counter goes from 0xFFFF to 0x0000 All three timers have separate internal prescaled counter clocks with either a common exter nal clock CTCLK or a prescaled version of the system clock The SoCs support nine Capture Registers The Capture Registers have edge selectable inputs and can generate an interrupt if desired The SoCs support six Compare Registers The Compare Regist...

Page 253: ...T INTERRUPT CONTROL TIMER 0 BLOCK TIMER 1 BLOCK TIMER 2 BLOCK INTERRUPT REQUEST ADVANCED PERIPHERAL BUS APB COMPARE REGISTER 2 LH754xx 16 TIMER 1 COUNTER INPUT CAPTURE 2 CAPTURE INPUT COMPARE OUTPUT INTERRUPT CONTROL INTERRUPT REQUEST COMPARE REGISTER 2 TIMER 2 COUNTER INPUT CAPTURE 2 CAPTURE INPUT COMPARE OUTPUT INTERRUPT CONTROL INTERRUPT REQUEST COMPARE REGISTER 2 ...

Page 254: ...TIMER0 CMP1 TIMER0 CNT TIMER0 INT_CNTRL TIMER0 CTCMP0A INTERNAL TO THE SoC EXTERNAL TO THE SoC CTCMP0B STATUS TIMER0 LH754xx 17 CAP0 L H CTCAP0A CTCAP0B CTCAP0C CTCAP0D CTCAP0E CAPTURE REGISTERS COUNTER REGISTER CONTROL REGISTER COMPARE REGISTERS INTERRUPT CONTROL REGISTER COMPARE CAPTURE CONTROL REGISTER ADVANCED PERIPHERAL BUS APB CTCLK CAP1 L H CAP2 L H CAP3 L H CAP4 L H ALL REGISTERS CONNECT T...

Page 255: ...RUPT CONTROL CIRCUIT INTERRUPT REQUEST CMP0 CNTRL TIMER0 CMP1 CNT INT_CNTRL CTCMPxA CTCMPxB STATUS LH754xx 18 CAP0 CTCAPxA CTCAPxB CAPTURE REGISTERS COUNTER REGISTER COMPARE REGISTERS INTERRUPT CONTROL REGISTER CONTROL REGISTER CTCLK CAP1 ADVANCED PERIPHERAL BUS APB ALL REGISTERS CONNECT TO THIS BUS INTERNAL TO THE SoC EXTERNAL TO THE SoC ...

Page 256: ... same Timer Control Register accessed in step 1 3 Start the counter by writing a 1 to the CS bit of the same Timer Control Register accessed in the previous steps If you select CTCLK in step 2 the timer increments the counter of the corresponding Timer Control Register on the third rising edge of system clock after a rising edge by CTCLK The pulse length of CTCLK must be equal to or longer than tw...

Page 257: ... rising edge of the internal count clock Figure 15 6 shows an example of a timer s count being cleared when the count reaches the compare match value This function is available with the compare value stored by the CMP1 Register The Compare Match Detect signal shown in Figure 15 6 can be output through either CTCCMP n A if the Timer Compare Register CMP0 is used CTCCMP n B if the Timer Compare Regi...

Page 258: ...set bit TC of the same Timer Control Register to 1 This setting clears the counter when the Timer Control Register value matches the CMP1 value The state of CTCMPnA matches the value of CMP1 starting from the time the counter matches the CMP1 Register until it matches the CMP0 Register The state of CTCMP n A then matches the value of CMP0 To create a proper PWM set the CMP0 bit of the Timer Contro...

Page 259: ...ers CMP1 0x0005 Period CMP0 0x0001 Period Timer 0 settings CMP_CAP_CTRL 15 1 PWM mode CMP_CAP_CTRL 14 1 Counter Clear CMP_CAP_CTRL 13 12 01 CMP1 CMP_CAP_CTRL 11 10 10 CMP0 Figure 15 8 PWM Output Signal Timing CNT REGISTER CMP1 REGISTER CMP0 REGISTER PWM OUTPUT CTCMPxA INTERNAL COUNT CLOCK 0x0004 0x0003 0x0005 0x0000 0x0001 0x0005 PERIOD 6 OFF TIME 0x0001 0x0002 0x0003 0x0004 0x0005 0x0000 0x0001 0...

Page 260: ... Capture Register 3 CAP4 0x2C R 0x0000 Timer 0 Capture Register 4 Table 15 2 Timer 1 Register Summary NAME ADDRESS OFFSET TYPE RESET VALUE DESCRIPTION CTRL 0x30 RW 0x0000 Timer 1 Control Register INT_CTRL 0x34 RW 0x0000 Timer 1 Interrupt Control Register STATUS 0x38 RW 0x0000 Timer 1 Status Register CNT 0x3C RW 0x0000 Timer 1 Counter Register CMP0 0x40 RW 0xFFFF Timer 1 Compare Register 0 CMP1 0x4...

Page 261: ...Reserved Read as zero 4 2 SEL Count Clock Select Specifies the system count clock 000 System clock 2 001 System clock 4 010 System clock 8 011 System clock 16 100 System clock 32 101 System clock 64 110 System clock 128 111 CTCLK The CS field bit 1 must be clear for changes to the SEL field to take effect 1 CS Start Stop Counter 0 Specifies whether counter 0 is stopped or started 0 Stops counter 0...

Page 262: ...utputs CTCMP0A is in PWM Mode 14 TC Timer 0 Counter Operation Determines whether the Timer 0 counter is to operate as either a free running counter or as an interval timer When set the counter clears upon matching the CMP1 Register for Timer 0 This operation is only available with the CMP1 Register Refer to Section 15 1 1 for a complete explanation 0 Inhibits counter clear operates as free running...

Page 263: ... rising edge falling edge both edges or ignores all changes of the input signal that is used as the capture trigger 00 Capture input CTCAP0C is ignored 01 Rising edge of CTCAP0C 10 Falling edge of CTCAP0C 11 Both edges of CTCAP0C 3 2 CAP1 Input Edge Select Selects the rising edge falling edge both edges or ignores all changes of the input signal that is used as the capture trigger 00 Capture input...

Page 264: ...ng Capture 3 Operation 0 No interrupt request occurs for capture 3 1 Interrupt request occurs for capture 3 5 CAP2_EN Timer 0 Interrupt Enable During Capture 2 Operation 0 No interrupt request occurs for capture 2 1 Interrupt request occurs for capture 2 4 CAP1_EN Timer 0 Interrupt Enable During Capture 1 Operation 0 No interrupt request occurs for capture 1 1 Interrupt request occurs for capture ...

Page 265: ...y writing a 1 to a bit that is not set does not affect the Status Register or interrupt Table 15 10 Status Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CAP4_ST CAP 3_ST CAP2_ST CAP1_ST CAP0_ST CMP1_ST CMP0_ST OVF_ST RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW ...

Page 266: ... changed Table 15 12 CNT Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TM0CNT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC4000 0x10 Table 15 13 CNT Register Definitions BITS FIELD NAME DESCRIPTION 31 16...

Page 267: ...h a trigger signal is generated Table 15 14 CMP n Registers BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TM0CMP RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR CMP0 0xFFFC4000 0x14 CMP1 0xFFFC4000 0x18 Table 15 15 CMP n ...

Page 268: ...input signal used to trigger the capturing operation is determined by setting the CMP_CAP_CTRL Register Table 15 16 CAP n Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CAP0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR CAP0 0x...

Page 269: ...C Timer 1 Operation This bit determines whether Timer 1 counter is to operate as either a free running counter or as an interval timer When set the counter clears upon matching CMP1 for Timer 1 This operation is only available with the CMP1 Register for Timer 1 Refer to Section 15 1 1 for a complete explanation 0 Inhibit counter clear operates as free running counter 1 Clear counter when CNT for T...

Page 270: ...gger 00 Capture input CTCAP1A is ignored 01 Rising edge of CTCAP1A 10 Falling edge of CTCAP1A 11 Both edges of CTCAP1A 4 2 SEL Count Clock Select 000 System clock 2 001 System clock 4 010 System clock 8 011 System clock 16 100 System clock 32 101 System clock 64 110 System clock 128 111 CTCLK The CS field bit 1 must be clear for changes to the SEL field to take effect 1 CS Start Stop Counter 1 0 S...

Page 271: ...Reserved Read as zero 4 CAP1_EN Timer 1 Interrupt Enable During Capture 1 Operation 0 No interrupt request occurs for Capture 1 1 Interrupt request occurs for Capture 1 3 CAP0_EN Timer 1 Interrupt Enable During Capture 0 Operation 0 No interrupt request occurs for Capture 0 1 Interrupt request occurs for Capture 0 2 CMP1_EN Timer 1 Interrupt Enable Upon Compare 1 0 No interrupt request occurs for ...

Page 272: ... is changed Writing a 0 to a status bit does not affect the corresponding interrupt Similarly writing a 1 to a bit that is not set does not affect the Status Register or Interrupt Table 15 22 Status Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CAP1_ST CAP0_...

Page 273: ...n be changed Table 15 24 CNT Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TM1CNT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC4000 0x3C Table 15 25 CNT Register Definitions BITS FIELD NAME DESCRIPTION 3...

Page 274: ...ch a trigger signal is generated Table 15 26 CMP n Registers BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TM1CMP RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR CMP0 0xFFFC4000 0x40 CMP1 0xFFFC4000 0x44 Table 15 27 CMP n...

Page 275: ...respectively The edge of the input signal used to trigger the capturing operation is determined by setting the CTRL Register Table 15 28 CAP n Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CAP1 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R...

Page 276: ...imer 2 Counter Operation This bit determines whether the counter is to oper ate as a free running counter or interval counter When set the counter clears upon matching CMP1 for Timer 2 This operation is only available with the CMP1 Register for Timer 2 Refer to Section 15 1 1 for a complete explanation of this feature 0 Inhibit counter clear operates as free running counter 1 Clear counter when CN...

Page 277: ...gger 00 Capture input CTCAP2A is ignored 01 Rising edge of CTCAP2A 10 Falling edge of CTCAP2A 11 Both edges of CTCAP2A 4 2 SEL Count Clock Select 000 System clock 2 001 System clock 4 010 System clock 8 011 System clock 16 100 System clock 32 101 System clock 64 110 System clock 128 111 CTCLK The CS field bit 1 must be clear for changes to the SEL field to take effect 1 CS Start Stop Counter 2 0 S...

Page 278: ... Reserved Read as zero 4 CAP1_EN Timer 2 Interrupt Enable During Capture Operation 0 No interrupt request occurs for Capture 1 1 Interrupt request occurs for Capture 1 3 CAP0_EN Timer 2 Interrupt Enable During Capture Operation 0 No interrupt request occurs for Capture 0 1 Interrupt request occurs for Capture 0 2 CMP1_EN Timer 2 Interrupt Enable Upon Compare 1 0 No interrupt request occurs for Com...

Page 279: ...d Writing a 0 to any of the status bits does not affect the corresponding interrupt Similarly writing a 1 to a bit that is not set does not affect the Status Register or interrupt Table 15 34 Status Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CAP1_ST CAP0_...

Page 280: ... be changed Table 15 36 CNT Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TM2CNT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC4000 0x5C Table 15 37 CNT Register Definitions BITS FIELD NAME DESCRIPTION 31...

Page 281: ...ch a trigger signal is generated Table 15 38 CMP n Registers BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TM2CMP RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR CMP0 0xFFFC4000 0x60 CMP1 0xFFFC4000 0x64 Table 15 39 CMP n...

Page 282: ... respectively The edge of the input signal used to trigger the capturing operation is determined by setting the CTRL Register Table 15 40 CAP n Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CAP2 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R ...

Page 283: ...1 Timer 2 Combined Interrupt a combined interrupt formed by ORing the two compare two capture and one overflow interrupts in Timer 2 Each Timer ORs its individual interrupt to provide a single combined interrupt If an individual interrupt is enabled and the corresponding interrupt condition compare cap ture or overflow occurs a combined interrupt also occurs Once the interrupt condition occurs the...

Page 284: ... interval and the count reloads from the pre set value after reaching zero The default timeout period is set to the minimum timeout of 216 system clock cycles The WDT is driven by the APB A built in protection mechanism guards against interrupt service failure The WDT can be programmed to trigger a System Reset on a timeout The WDT can be programmed to trigger an interrupt on the first timeout the...

Page 285: ... to be issued by the RCPC There are 16 selectable time intervals for a time out of 216 through 231 system clock cycles See Chapter 9 for a complete description about reset generation 16 3 WDT Programmer s Model The base address for the WDT is WDT Base Address 0xFFFE3000 16 3 0 1 WDT Register Summary Table 16 1 WDT Register Summary NAME ADDRESS OFFSET TYPE RESET VALUE DESCRIPTION CTRL 0x00 R W 0x00...

Page 286: ...t period the new value will not come into affect un til a counter reset command has been issued or when the WDT times out 3 FRZ Freeze EN Bit set only 0 Do not stop the EN bit from being cleared when the watchdog is enabled 1 Stop the EN bit from being cleared when the watchdog is enabled This avoids accidental write operations that disable the watchdog and can only be cleared by a System Reset 2 ...

Page 287: ...0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD WDCNTR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW W W W W W W W W W W W W W W W W ADDR 0xFFFE3000 0x04 Table 16 5 CNTR Register Definitions BITS NAME DESCRIPTION 31 16 Reserved Writing to these bits has no effect Reading returns 0 15 0 WDCNTR Time out Count Down Writing 0x1984 to this register causes the counter to ...

Page 288: ... 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFE3000 0x08 Table 16 7 STR Register Definitions BITS NAME DESCRIPTION 31 8 Reserved Writing to these bits has no effect Reading returns 0 7 nWDINTR nWDINTR Interrupt Status 1 WDT interrupt has triggered 0 WDT interrupt has not triggered 6 Reserved Always reads as 1 5 4 RSP Response Status Holds the required response as set in CTRL Regis ter de...

Page 289: ... 16 9 CNT0 Register Definitions BITS NAME DESCRIPTION 31 8 Reserved Writing to these bits has no effect Reading returns 0 7 0 Counter Sub Section 0 Current Count Value Holds bits 7 0 of the current count value Table 16 10 CNT1 Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4...

Page 290: ...6 13 CNT2 Register Definitions BITS NAME DESCRIPTION 31 8 Reserved Writing to these bits has no effect Reading returns 0 7 0 Counter Sub Section 2 Current Count Value Holds bits 23 16 of the current count value Table 16 14 CNT3 Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 ...

Page 291: ...d intervals is achieved using a 1 Hz clock input to the RTC Figure 17 1 shows a block diagram of the RTC 17 1 RTC Features The RTC provides the following features AMBA APB interface 32 bit up counter with programmable load Programmable 32 bit match Compare Register Software maskable interrupt that is set when the Counter and Compare Registers have identical values Figure 17 1 RTC Block Diagram LH7...

Page 292: ...ter value read DR0 first This is because DR1 contains the value of the upper 16 bits when DR0 was last read rather than the current value of the upper 16 bits When the counter reaches the maximum value 0xFFFFFFFF it wraps to zero and continues incrementing For more information about these registers refer to Section 17 3 2 1 and Section 17 3 2 2 Writing to MR0 and MR1 programs the least significant...

Page 293: ...ng normal operation Table 17 1 RTC Register Summary NAME ADDRESS OFFSET TYPE RESET VALUE DESCRIPTION DR0 0x00 R Lower 16 bit Data Register DR1 0x04 R Upper 16 bit Data Register MR0 0x08 RW Lower 16 bit Match Register MR1 0x0C RW Upper 16 bit Match Register STAT EOI 0x10 RW Interrupt Status Register read Interrupt Clear Register write LR0 0x14 RW Lower 16 bit Counter Load Register LR1 0x18 RW Upper...

Page 294: ...with the current value of the upper 16 bits of the counter NOTE The reset value of this register s bits is indeterminate Table 17 2 DR0 Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RTCDR0 RESET RW R R R R R R R R R R R R R R R R ADDR 0xFFFE0000 0x00 Table 17 3 DR0 Register Definitions BIT...

Page 295: ...en the DR0 and the DR1 Registers due to a counter rollover NOTE The reset value of this register s bits is indeterminate Table 17 4 DR1 Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RTCDR1 RESET RW R R R R R R R R R R R R R R R R ADDR 0xFFFE0000 0x04 Table 17 5 DR1 Register Definitions BIT...

Page 296: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RTCMR0 RESET RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE0000 0x08 Table 17 7 MR0 Register Definitions BIT NAME DESCRIPTION 31 16 Reserved 15 0 RTCMR0 RTC Match Register 0 Specifies the lower 16 bit Match Register Table 17 8 MR1 Register BIT ...

Page 297: ... W W W W W W W W W W W W W W W BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RTCEOI RESET RW W W W W W W W W W W W W W W W W ADDR 0xFFFE0000 0x10 Table 17 11 STAT EOI Register Definitions Write Operations BITS NAME DESCRIPTION 31 0 RTCEOI End Of Interrupt A write to this register clears RTCINTR regardless of the data value written Table 17 12 STAT EOI Register Read Operations BIT 31 30 29 28 27 ...

Page 298: ...lock follows a write operation to LR1 Read operations return the last value written NOTE The reset value of this register s bits is indeterminate Table 18 LR0 Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RTCLR0 RESET RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFE0000 0x14 ...

Page 299: ...n to first followed by LR1 when the counter is to be reinitialized Reads return the last written value NOTE The reset value of this register s bits is indeterminate Table 20 LR1 Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RTCLR1 RESET RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW AD...

Page 300: ...TRL Register To enable the interrupt set bit 0 of the CTRL Register to HIGH The status of the interrupt mask can be read via the CTRL Register The RTCINTR status can be read from bit 0 in the STAT Register Writing to EOI clears the RTCINTR flag Table 22 CTRL Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R B...

Page 301: ...ata and one for receiving data The transmit FIFO takes data written to it and transmits it on the serial interface The receive FIFO parallellizes the serial data stream and presents it in a FIFO for access by other devices If the receive FIFO is not empty the SSP can assert an interrupt after a specified number of clock ticks elapses following the start of a receive transfer This feature permits i...

Page 302: ...KDIV TX RX params SSPCLKDIV INTERRUPT GENERATOR CLOCK PRESCALER Rx FIFO 16 BITS WIDE 8 BITS DEEP Tx FIFO 16 BITS WIDE 8 BITS DEEP BnRES PSEL PENABLE PWRITE SSPTXINTR SSPRXINTR SSPRORINTR SSPRXINTR SSPRORINTR SSPTXINTR SSPTXINTR SSPRXINTR SSPRORINTR SSPOE SSPTXD SFRM SCLK SSPRXD SSPINTR SYSTEM CLOCK SSPCLK_RCPC PADDRH 7 6 PWDATAin 15 0 RxFRdData 15 0 TxFRdDataIn 15 0 RxWrData 15 0 PADDRL 4 2 PWDATA...

Page 303: ...these modes For all three formats the serial clock SSPCLK is held inactive while the SSP is idle and transitions at the programmed frequency only during active transmission of data The SSPCLK pin can be HIGH during idle in SPI Mode if the SPO bit in the Control Register is set For Motorola SPI and National Semiconductor Microwire frame formats the serial frame SSPFRM pin is active LOW and asserted...

Page 304: ...400 01 10 11 Preliminary User s Guide 18 4 6 17 03 18 3 SSP Timing Waveforms Figure 18 2 shows the standard set of SSP timing waveforms Figure 18 2 SSP Timing Waveform SSPCLK SSPFRM SSPTX SSPRX tOVSSPFRM tOVSSPTX tISSPRX 754xx 49 ...

Page 305: ...tinuous Modes Figure 18 3 through Figure 18 6 show the Motorola SPI frame format for single data trans fers continuous data transfers and when SPH equals 0 or 1 Figure 18 3 Motorola SPI Frame Format Single Transfer Figure 18 4 Motorola SPI Frame Format Continuous Transfer SSPRX NOTES 1 Single transfer SPH 0 SPO 0 2 Q Undefined SSPTX SSPFRM SSPCLK 4 to 16 BITS MSB MSB LSB Q LSB LH754xx 31 NOTE Cont...

Page 306: ... SPI Frame Format with SPH 0 Figure 18 6 Motorola SPI Frame Format with SPH 1 SSPFRM SSPRX from slave SSPTX from master SSPCLK SPO 1 SSPCLK SPO 0 NOTE Q Undefined MSB MSB LSB LSB Q LH754xx 33 SFRM SSIRxD from slave SSITxD from master SCLK SPO 1 SCLK SPO 0 NOTE Q Undefined MSB LSB MSB Q LSB LH754xx 34 ...

Page 307: ...ame format the SSP outputs data on the rising edge of the clock and latches input data on the rising edge of the clock Figure 18 7 shows the Texas Instruments DSP format for a single transfer Figure 18 8 shows the same format for continuous transfers Figure 18 7 Texas Instruments Synchronous Serial Frame Format Single Transfer Figure 18 8 Texas Instruments Synchronous Serial Frame Format Continuou...

Page 308: ...sponds with the requested data The returned data can be 4 to 16 bits long making the total frame 13 to 25 bits long During reception data goes through a serial to parallel conversion before being placed into the receive FIFO The data is then read out via the AMBA APB interface Figure 18 9 shows the National Semiconductor Microwire format for a single transfer Figure 18 10 shows this format for con...

Page 309: ... 10 11 Preliminary User s Guide Synchronous Serial Port 6 17 03 18 9 Figure 18 9 Microwire Frame Format Single Transfer SSPCLK SSPFRM SSPTX SSPRX MSB LSB MSB LSB 8 BIT CONTROL 4 TO 16 BITS OUTPUT DATA LH754xx 37 ...

Page 310: ... Port LH75400 01 10 11 Preliminary User s Guide 18 10 6 17 03 Figure 18 10 Microwire Frame Format Continuous Transfers MSB MSB MSB LSB LSB 8 BIT CONTROL 4 TO 16 BITS OUTPUT DATA SSPCLK SSPFRM SSPTX SSPRX LH754xx 38 LSB 0 ...

Page 311: ...5 1 SSP Register Summary Table 18 2 Register Summary NAME ADDRESS OFFSET TYPE RESET VALUE DESCRIPTION CTRL0 0x000 RW 0x0000 Control Register 0 CTRL1 0x004 RW 0x0000 Control Register 1 DR 0x008 RW 0x0000 Receive FIFO Read Transmit FIFO Write SR 0x00C R 0x03 Status Register CPSR 0x010 RW 0x00 Clock Prescale Register IIR ICR 0x014 RW 0x0 Interrupt Identification Register read Interrupt Clear Register...

Page 312: ...gister Definitions BITS NAME DESCRIPTION 31 16 Reserved Writing to these bits has no effect Reading returns 0 15 8 SCR Serial Clock Rate The SCR value is used to generate the transmit and receive bit rate of the SSP 7 SPH SSPCLK Phase Applicable to Motorola SPI frame format only 6 SPO SSPCLK Polarity Applicable to Motorola SPI frame format only 5 4 FRF Frame Format 00 Motorola SPI frame format 01 ...

Page 313: ...us Serial Port Enable 0 SSP operation is disabled 1 SSP operation is enabled 3 LBM Loopback Mode 0 Normal serial port operation enabled 1 Output of transmit serial shifter is connected to input of receive serial shifter internally 2 RORIE Receive FIFO Overrun Interrupt Enable 0 Overrun detection is disabled Overrun condition does not generate the SSPRORINTR interrupt Clearing this bit to zero also...

Page 314: ...National Microwire frame format the default size for transmit data is eight bits the most significant byte is ignored The receive data size is controlled by the programmer The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in Control Register 1 is set to zero refer to Section 18 5 2 2 This allows the software to fill the transmit FIFO before enabling the SSP When using Te...

Page 315: ... 0 0 0 0 0 1 1 RW R R R R R ADDR 0xFFFC6000 0x00C Table 18 10 SR Register Definitions BITS NAME DESCRIPTION 31 16 Reserved Writing to these bits has no effect Reading returns 0 15 5 Reserved Write as 0 Unpredictable behavior when read 4 BSY SSP Busy Flag 0 SSP is idle 1 SSP is transmitting and or receiving a frame or the transmit FIFO is non empty 3 RFF Receive FIFO Full 0 Receive FIFO is not full...

Page 316: ...es after Reset Table 18 11 CPSR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CPSDVSR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW W W W W W W W W RW RW RW RW RW RW RW R ADDR 0xFFFC6000 0x010 Table 18 12 CPSR Register Definitions BITS NAME DESCRIPTION 31 16 Rese...

Page 317: ...er Read Characteristic BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RORIS TIS RIS RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFC6000 0x014 Table 18 14 IIR ICR Register Definitions Read Operation BITS NAME DESCRIPTION 31 16 Reser...

Page 318: ...eive Overrun Interrupt A write to these bits clears the Receive Overrun Interrupt regardless of the data value written Table 18 17 RXTO Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RXTO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW ...

Page 319: ...individual interrupt sources can be read from the IIR Register 18 5 3 1 Receive Interrupt SSPRXINTR is the Receive Interrupt This interrupt is asserted when there are four or more valid entries in the receive FIFO The interrupt is cleared by reading the receive FIFO until there are three or fewer entries 18 5 3 2 Transmit Interrupt SSPTXINTR is the Transmit Interrupt This interrupt is asserted whe...

Page 320: ...num ber of HCLK periods programmed in the RXTO Register 18 5 3 5 SSPINTR The SSPRXINTR SSPTXINTR SSPRORINTR and SSPRXTOINTR interrupts are also combined into the single output SSPINTR This interrupt is an OR function of the individual interrupt sources This output can be connected to the system interrupt controller to pro vide another level of masking on a per peripheral basis The combined SSP Int...

Page 321: ...6 bytes to be stored independently in both transmit and receive modes FIFO depth is 16 If a FIFO is disabled a 1 byte holding register is used Figure 19 1 shows a block diagram of UART0 and UART1 Figure 19 1 UART0 and UART1 Block Diagram LH754xx 13 APB INTERFACE AND REGISTER BLOCK BAUD RATE GENERATOR TRANSMITTER 16 12 RECEIVE FIFO BAUD16 RECEIVER UARTTXINTR INTERRUPT GENERATION DMA INTERFACE TRANS...

Page 322: ...system clock 19 2 UART0 and UART1 Theory of Operation All UART Control and Status Registers can be accessed through the APB During trans mission data writes to the transmit FIFO through the APB interface When data writes to the transmit FIFO The UART causes the data frame to start transmitting with the parameters indicated in register LCR_H if the UART is enabled Data continues to transmit until n...

Page 323: ... the UART stores the received data frames and associ ated status bits in the receiver FIFO 19 2 2 Status Conditions UARTs 0 and 1 adhere to the following status conditions If a UART fails to detect a 1 for all programmed stop bit periods following a data frame the UART sets the framing error status for that frame Enabling parity error detection causes the UART to compare the parity bit in each fra...

Page 324: ... request is issued when the transmit channel FIFO falls below its low water mark The request is reissued if the FIFO remains below that level when the DMA request has been serviced or the next time that the FIFO falls below that level DMA requests are masked when the UART issues an error interrupt If the UART is in the FIFO Disabled Mode only the DMA Single Transfer Mode can operate since only one...

Page 325: ... Register Summary NAME ADDRESS OFFSET TYPE RESET VALUE DESCRIPTION DR 0x000 RW 0x Data read or written from the interface It is 12 bits wide on a read and 8 on a write RSR ECR 0x004 RW 0x0 Receive Status Register read Error Clear Register write 0x008 0x014 Reserved FR 0x018 R 0x00000090 Flag Register read only 0x01C 0x020 Reserved IBRD 0x024 R 0x0000 Integer Baud Rate Divisor Register FBRD 0x028 R...

Page 326: ...led data is stored in the Transmitter Holding Register the bottom word of the transmit FIFO A read to this register pops the first word from the receive FIFO This word consists of the received character and the associated error bits Table 19 2 DR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 ...

Page 327: ... break occurs only one 0 character is loaded into the FIFO The next character is only enabled after the receive data input goes to a 1 marking state and the next valid start bit is received 9 PARITY ERROR Parity Error 1 The parity of the received data character does not match the parity selected as defined by bits 2 and 7 of the LCR_H Register see Section 19 3 1 9 In FIFO Mode this error is associ...

Page 328: ...his read sequence cannot be reversed because the RSR Register is updated only when a read occurs from the DR Register However the status information can also be obtained by reading the DR Register Table 19 4 and Table 19 5 describe the RSR ECR Register for write operations Table 19 4 RSR ECR Register Write Operations BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0...

Page 329: ...ta is written when the FIFO is full only the contents of the shift register are overwritten The CPU must now read the data in order to empty the FIFO 2 BREAK ERROR Break Error 1 A break condition was detected indicating that the received data input was held LOW for longer than a full word transmission time defined as start data parity and stop bits This bit is cleared to 0 after a write to ECR In ...

Page 330: ...transmit FIFO is empty 6 RECEIVE FIFO FULL Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the LCR_H Register see Section 19 16 FIFO disabled This bit is set when the Receive Holding Register is full FIFO enabled RXFF bit is set when the receive FIFO is full 5 TRANSMIT FIFO FULL Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the L...

Page 331: ...uency must be selected ƒUARTCLK MIN 16 baud_rate MAX ƒUARTCLK MAX 16 65535 baud_rate MIN This frequency must be within the required error limits for all baud rates to be used and must not be more than 5 3 times faster than the frequency of the system clock Table 19 10 Updating Register Contents TO UPDATE PERFORM The IBRD or FBRD Register A LCR_H write operation at the end Both the IBRD and FBRD Re...

Page 332: ...R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD BAUD RATE INTEGER RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR UART0 0xFFFC0000 0x024 UART1 0xFFFC1000 0x024 Table 19 12 IBRD Register Definitions BIT NAME DESCRIPTION 31 16 Reserved 15 0 BAUD RATE INTEGER Integer Baud Rate Divisor This value is used with the Fractional Baud Rate Diviso...

Page 333: ...R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD BAUD RATE FUNCTION RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR UART0 0xFFFC0000 0x028 UART1 0xFFFC1000 0x028 Table 19 14 FBRD Register Definitions BIT NAME DESCRIPTION 31 16 Reserved Read as zero 5 0 BAUD RATE FUNCTION Fractional Baud Rate Divisor This value is used with ...

Page 334: ...ud rate 4 106 16 1 078 231 911 6 Error 231 911 230 400 230 400 100 0 656 The maximum error using a 6 bit FBRD Register 1 64 100 1 56 This occurs when m 1 and the error is cumulative over 64 clock ticks 19 3 1 8 Typical Bit Rates and Their Corresponding Divisor Table 19 15 shows some typical bit rates and their corresponding divisor given the UART Clock Frequency of 14 7456 MHz Table 19 15 Bit Rate...

Page 335: ...the current character is complete Table 19 16 is a truth table for the SPS EPS and PEN bits of the LCTRL_H Register Table 19 16 LCTRL_H Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD STICK PARITY SELECT WORDLENGTH ENABLE FIFOS TWO STOP BITS SELECt EVEN PARITY...

Page 336: ...e frame The receive logic always checks for received stop bits regardless of whether there are one or two 2 EVEN PARITY SELECT Even Parity Select Bits 7 2 and 1 work together to set up the parity See Table 19 18 1 PARITY ENABLE Parity Enable Bits 7 2 and 1 work together to set up the parity See Table 19 18 0 SEND BREAK 1 A LOW level is continuously output on the UARTTXD output after completing tra...

Page 337: ...UART1 0xFFFC1000 0x030 Table 19 20 CTRL Register Definitions BIT NAME DESCRIPTION 31 10 Reserved Do not modify 9 RECEIVE ENABLE Receive Section 1 Enables the receive section of the UART When the UART is disabled in the middle of reception it completes the current character before stopping 8 TRANSMIT ENABLE Transmit Section 1 Enables the transmit section of the UART When the UART is disabled in the...

Page 338: ...ET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RECEIVE INTERRUPT FIFO LEVEL SELECT TRANSMIT INTERRUPT FIFO LEVEL SELECT RESET 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 RW R R R R R R R R R R RW RW RW RW RW RW ADDR UART0 0xFFFC0000 0x034 UART1 0xFFFC1000 0x034 Table 19 22 IFLS Register Definitions BIT NAME DESCRIPTION 31 6 Reserved Do not...

Page 339: ...0 0 0 0 0 0 RW R R R R R RW RW RW RW RW RW RW R R R R ADDR UART0 0xFFFC0000 0x038 UART1 0xFFFC1000 0x038 Table 19 24 IMSC Register Definitions BITS NAME DESCRIPTION 31 11 Reserved Do not modify 10 OVERRUN ERROR INTERRUPT MASK Overrun Error Interrupt Mask Write values 0 Clears the mask 1 Sets the mask of the OEIM interrupt When Read returns the current mask for the OEIM interrupt 9 BREAK ERROR INTE...

Page 340: ...interrupt 5 TRANSMIT INTERRUPT MASK Transmit Interrupt Mask Write values 0 Clears the mask 1 Sets the mask of the TXIM interrupt When Read returns the current mask for the TXIM interrupt 4 RECEIVE INTERRUPT MASK Receive Interrupt Mask Write values 0 Clears the mask 1 Sets the mask of the RXIM interrupt When Read returns the current mask for the RXIM interrupt 3 0 Reserved Do not modify Table 19 24...

Page 341: ...s BITS NAME DESCRIPTION 31 11 Reserved Do not modify 10 OVERRUN ERROR INTERRUPT STATUS Raw Interrupt State Specifies the raw interrupt state pri or to masking of the UARTOEINTR interrupt 9 BREAK INTERRUPT STATUS Break Interrupt Status Specifies the raw interrupt state prior to masking of the UARTBEINTR interrupt 8 PARITY ERROR INTERRUPT STATUS Parity Error Interrupt Status Specifies the raw interr...

Page 342: ...eserved Do not modify 10 OVERRUN ERROR MASKED INTERRUPT STATUS Overrun Error Masked Interrupt Status Specifies the masked interrupt state after masking of the UARTOEINTR interrupt 9 BREAK ERROR MASKED INTERRUPT STATUS Break Error Masked Interrupt Status Specifies the masked interrupt state after masking of the UARTBEINTR interrupt 8 PARITY ERROR MASKED INTERRUPT STATUS Parity Error Masked Interrup...

Page 343: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R W W W W W W W R R R R ADDR UART0 0xFFFC0000 0x044 UART1 0xFFFC1000 0x044 Table 19 30 ICR Register Definitions BIT NAME DESCRIPTION 31 15 Reserved Do not modify 10 OVERRUN ERROR INTERRUPT CLEAR Overrun Error Interrupt Clear Clears the UARTOEINTR interrupt 9 BREAK ERROR INTER RUPT CLEAR Break Error Interrupt Clear Clears the UARTBEINTR in terrupt 8 PARITY ...

Page 344: ...red to 0 on System Reset Table 19 31 DMACTRL Register Definitions BIT NAME DESCRIPTION 15 3 Reserved Do not modify 2 DMA ON ERROR DMA on Error 1 Disables the DMA receive request output UARTRXDMABREQ when the UART Error Interrupt is asserted 1 TRANSMIT DMA ENABLE Transmit DMA Enable 1 Enables the DMA for the transmit FIFO 0 RECEIVE DMA ENABLE Receive DMA Enable 1 Enables the DMA for the receive FIF...

Page 345: ...transmit FIFO the interrupt is not set The interrupt is only set after written data exits the single location of the transmit FIFO leaving the FIFO empty 19 3 2 3 UARTINTR The UARTINTR interrupt is the combined interrupt for UART0 and UART1 It is asserted if one or more of the other interrupts are asserted Table 19 32 UARTRXINTR State FIFO EVENT RECEIVE INTERRUPT STATUS FIFOs are enabled and the r...

Page 346: ...itted to the peripheral device The CPU reads and writes data and control status information through the AMBA APB interface The transmit and receive paths are buffered with internal FIFO memories that support a programmable depth from 1 to 4 Figure 20 1 shows a block diagram of the UART Figure 20 1 UART2 Block Diagram LH754xx 14 BUS INTERFACE Tx FIFO TRANSMITTER APB INTERRUPT TO VIC BAUD RATE GENER...

Page 347: ...tor are configurable A single interrupt that can be triggered by transmit and receive FIFO thresholds receive errors control character or address marker reception or timer timeout Generation and detection of breaks during UART transactions Support for local loopback remote loopback and auto echo modes µLAN Address Mode 20 2 UART2 Theory of Operation All Control and Status Registers for the UART ca...

Page 348: ...UART transfers the received data and the frame status to the receiver FIFO This buffer can have a depth of either four words FIFO Mode or one word Character Mode The UART receiver Synchronizes the incoming data Passes it through a digital filter to filter out the spikes Samples the UART2RX pin either three or seven times at a frequency of 16X the bit rate to generate the data bit The number of sam...

Page 349: ...er repeats one of the following sequences until all data bits any parity bit and all stop bits are detected 3 16 Sampling Mode 1 Wait 14 16ths of a bit period then sample the input 2 Wait 1 16th of a bit period then sample the input 3 Wait 1 16th of a bit period then sample the input 4 Choose the majority value of the three samples as its input value for that bit period 7 16 Sampling Mode 1 Wait 1...

Page 350: ... bit is set 20 2 3 Disabling the Loading of Incoming Characters UART2 provides the option of disabling the loading of incoming characters into the receiver FIFO by using the UNLOCK LOCK FIFO commands When the receiver FIFO is locked received characters do not load into the FIFO and can be lost if another character is received The UNLOCK LOCK FIFO commands are useful when the CPU is not willing to ...

Page 351: ...n these formulas divisorA is defined by the BAH and BAL Registers divisorB is defined by the BBH and BBL Registers The divisor range for the cascaded baud rate generators is 1 to 4 294 836 225 When a baud rate generator is configured as a timer it counts down from its divisor count value BAH BAL or BBH BBL to 1 once it is enabled A maskable Timer Expired interrupt is generated upon terminal count ...

Page 352: ...e 20 3 1 1 Register Bank 0 DLAB Divisor Latch Access Bit is a bit in the Line Configure Register LCR See Section 20 3 2 7 Table 20 1 Register Bank 0 Default On Reset NAME ADDRESS OFFSET DLAB TYPE RESET VALUE DESCRIPTION TXD 0x00 0 W Transmit Buffered Data Register RXD 0x00 0 R 0x00 Receive Buffered Data Register BAL 0x00 1 RW 0x02 BRGA Divisor Least Significant Byte Register The DLAB bit in the LC...

Page 353: ...CTRL 0x10 W Loopback Control Register FLR 0x10 R 0x00 FIFO Level Register RCM 0x14 W Receive Command Register RST 0x14 R 0x00 Receive Machine Status Register TCM 0x18 W Transmit Command Register 0x18 R Reserved ICM 0x1C W Internal Command Register GSR 0x1C R 0x12 General Status Register Table 20 3 Register Bank 2 NAME ADDRESS OFFSET DLAB TYPE RESET VALUE DESCRIPTION 0x00 Reserved FMD 0x04 RW 0x00 ...

Page 354: ...Register BBL 0x00 1 RW 0x05 BRGB Divisor LSB Register The DLAB bit in the LCR Register needs to be set to access this register BBH 0x04 1 RW 0x00 BRGB Divisor MSB Register The DLAB bit in the LCR Register needs to be set to access this register GIR 0x08 RW 0x01 General Interrupt Register Bank Register same register as in bank 0 BBCF 0x0C RW 0x84 BRGB Configuration Register 0x10 Reserved 0x14 Reser...

Page 355: ...it FIFO NOTE The reset value of this register s bits is indeterminate Table 20 5 TXD Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD D7 D6 D5 D4 D3 D2 D1 D0 RESET RW R R R R R R R R W W W W W W W W ADDR 0xFFFC2000 0x00 Table 20 6 TXD Register Definitions BITS NAME DESCRIPTION 31 8 Reserved D...

Page 356: ...gister BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD D7 D6 D5 D4 D3 D2 D1 D0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFC2000 0x00 Table 20 8 RXD Register Definitions BITS NAME DESCRIPTION 31 8 Reserved Do not modify Read as ze...

Page 357: ...alues for this register range from 2 to 65 535 Table 20 9 BAL Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD D7 D6 D5 D4 D3 D2 D1 D0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 RW R R R R R R R R RW RW RW RW RW RW RW RW ADDR 0xFFFC2000 0x00 Table 20 10 BAL Register...

Page 358: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD D7 D6 D5 D4 D3 D2 D1 D0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R RW RW RW RW RW RW RW RW ADDR 0xFFFC2000 0x04 Table 20 12 BAH Register Definitions BITS NAME DESCRIPTION 31 8 Reserved Do not modify Read as zer...

Page 359: ...8 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TIE TxIE RxIE TFIE RFIE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R RW RW R RW RW RW ADDR 0xFFFC2000 0x04 Table 20 14 GER Register Definitions BITS NAME DESCRIPTION 31 6 Reserved Do not modify Read as zero 5 TIE Timers...

Page 360: ... 0 1 RW R R R R R R R R R RW RW R R R R R ADDR 0xFFFC2000 0x08 Table 20 16 GIR Register Definitions BITS NAME DESCRIPTION 31 7 Reserved Do not modify Read as zero 6 Bank 1 Bank 1 Works with bit 5 to indicate the use of a specific type of bank Possibilities are 8250A 16450 Compatible Bank Bank 0 General Work Bank Bank 1 General Configuration Bank Bank 2 Baud Rate Generation Configuration Bank Bank ...

Page 361: ...neral Work Bank Bank 1 1 0 General Configuration Bank Bank 2 1 1 Baud Rate Generation Configuration Bank Bank 3 Table 20 18 Pending Interrupt Status Bits 3 1 BI2 BI1 BI0 PENDING INTERRUPT 0 0 0 Not Used 0 0 1 Transmit FIFO Interrupt lowest priority 0 1 0 Receive FIFO Interrupt 0 1 1 Receiver Interrupt 1 0 0 Transmitter Interrupt 1 0 1 Timer Interrupt highest priority ...

Page 362: ... the BBL and BBH Registers in Bank 3 6 SBK UART2TX Pin 1 Forces the UART2TX pin LOW The UART2TX pin remains LOW regardless of all activities until this bit is reset 5 PM2 Parity Mode Works with PM1 PM0 and bit 2 from the Transmit Machine Mode Register to define the supported parity mode See Table 20 21 4 PM1 Parity Mode Works with PM2 PM0 and bit 2 from the Transmit Machine Mode Register to define...

Page 363: ...Parity 1 0 0 0 Odd Parity 1 0 0 1 Even Parity 1 0 1 0 High Parity 1 0 1 1 Low Parity 1 1 0 0 Software Parity Table 20 22 Stop Bit Lengths SBL2 SBL1 SBL0 STOP BIT LENGTH 0 0 0 4 4 0 0 1 6 4 or 8 4 0 1 0 3 4 0 1 1 4 4 1 0 0 5 4 1 0 1 6 4 1 1 0 7 4 1 1 1 8 4 Table 20 23 Character Bit Lengths NBCL CL1 CL0 CHARACTER LENGTH 0 0 0 5 Bits 0 0 1 6 Bits 0 1 0 7 Bits 0 1 1 8 Bits 1 0 0 9 Bits ...

Page 364: ...D RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD LC RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R RW R R R R ADDR 0xFFFC2000 0x10 Table 20 25 MCTRL Register Bank 1 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIEL...

Page 365: ...e that the Transmit Machine txM is empty or disabled 5 TFST Transmit FIFO Status Functionally identical to the TFIR bit of the GSR Register It indi cates that the Transmit FIFO level is equal to or below the Transmit FIFO Threshold To dis able the transmit FIFO status from being reflected in GIR either Write a zero to the TFIE bit of the GER Register or Use the Tx FIFO HOLD INTERRUPT logic When th...

Page 366: ...th zeros In µLAN Mode this register contains the 8 bit station address for recognition In this mode only incoming address characters that is characters with the address bit set are compared to these registers The PCRF bit in the RST Register is not set when an Address or Control Character match occurs Table 20 29 ACTRL0 Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0...

Page 367: ...ts is indeterminate Table 20 31 TXF Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD µLAN SP D8 RESET RW R R R R R R R R W W W W W W W W ADDR 0xFFFC2000 0x04 Table 20 32 TXF Register Definitions BITS NAME DESCRIPTION 31 8 Reserved Do not modify Read as zero 7 µLAN Address Marker Bit Specifies...

Page 368: ... has no parity or framing error The parity error is not included in the Software Parity Mode 5 RXN Received Character Noisy Indicates that the received character was noisy and had no identical samples for at least one of its bits 4 RPE Receive Character Parity Error Indicates that the RxD character had a parity error However in Software Parity Mode the received parity bit is held as is For informa...

Page 369: ...1 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TGB TGA STB STA RESET 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 RW ADDR 0xFFFC2000 0x0C Table 20 36 TMCTRL Register Definitions BITS NAME DESCRIPTION 31 6 Reserved Do not modify 5 TGB Timer B Gate Serves as a gate for Timer B operation 0 Disables counting 1 Enables counting 4 TGA Timer A Gate Serv...

Page 370: ... RESET 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFC2000 0x0C Table 20 38 TMST Register Definitions BITS NAME DESCRIPTION 31 6 Reserved Do not modify Read as zero 5 GBS Gate B State Indicates the counting state of the software gate of Timer B as written through the TMCTRL Register see Section 20 3 2 13 0 Disables counting 1 Enables counting This bit does not genera...

Page 371: ...12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RFL2 RFL1 RFL0 TFL2 TFL1 TFL0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFC2000 0x10 Table 20 40 FLR Register Definitions BITS NAME DESCRIPTION 31 7 Reserved Do not modify Read as zero 6 4 RFL2 RFL1 RFL0 Receive FIFO Level of Occupancy Indicates the number of char acters in the Receive FIFO The valid range is from zero 000 t...

Page 372: ...ead as zero 7 RXE Receive Enable 1 Enables the reception of characters 6 RXDI Receive Disable 1 Disables the reception of data on RXD pin RxDI takes priority over RxE in disabling the reception of characters 5 FRM Flush Receive Machine 1 Resets the receiver logic except registers and FIFOs enables reception and unlocks the receive FIFO 4 FRF Flush Receive FIFO Setting this bit clears the Rx FIFO 3...

Page 373: ...ero 7 CRF Control Address Character Received 1 Causes an interrupt if a control character or address character is received In µLAN Mode this interrupt indicates that an address character has been received In Normal Mode this interrupt indicates that a standard ASCII or EBCDIC control character has been received 6 PCRF Programmed Control Address Character Received 1 Causes an interrupt when an addr...

Page 374: ... R R R R R W W W W ADDR 0xFFFC2000 0x18 Table 20 46 TCM Register Definitions BITS NAME DESCRIPTION 31 4 Reserved Do not modify Read as zero 3 FTM Flush Transmit Machine 1 Resets the transmit machine logic except for the registers and FIFO and enables transmission 2 FTF Flush Transmit FIFO 1 Clears the Tx FIFO Data remains in the Tx FIFO until this bit is set The FIFO starts out flushed at reset 1 ...

Page 375: ... 5 4 3 2 1 0 FIELD INTA STC RESET RW W W W W W W W W W W W W W W W W ADDR 0xFFFC2000 0x1C Table 20 48 ICM Register Definitions BITS NAME DESCRIPTION 31 4 Reserved Do not modify Read as zero 3 INTA Interrupt Acknowledge This bit provides for an explicit acknowledgement of the device interrupt request This bit is provided for Manual Acknowledge Mode see Section 20 3 3 1 This bit forces the INT pin i...

Page 376: ... R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TIR TXIR RXIR TFIR RFIR RESET 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFC2000 0x1C Table 20 50 GSR Register Definitions BITS NAME DESCRIPTION 31 6 Reserved Do not modify Read as zero 5 TIR Timers Interrupt Request Indicates that a timer has expired See Section 20 3 2 14 4 TXIR Transmit Mac...

Page 377: ...BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RFT1 RFT0 TFT1 TFT0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R RW RW R R RW RW ADDR 0xFFFC2000 0x04 Table 20 52 FMD Register Definitions BITS NAME DESCRIPTION 31 6 Reserved Do not modify Read as zero 5 4 RFT1 RFT0 Receive FIFO Threshold When the number of characters in the Rx FIFO is greater than the number indicated by these bits t...

Page 378: ... Echo Mode only Echo Mode select is set in the IMD Register 6 CED Control Character Echo Disable 1 Disables echo of characters recognized as control characters or address characters in µLAN Mode valid in Echo Mode only The control character or address character is set in the ACR0 Register Echo Mode select is set in the IMD Register 5 NBCL Nine bit Length Works with bits 1 0 of the CLR Register to ...

Page 379: ...31 4 Reserved Do not modify Read as zero 3 Reserved Do not modify Read as one 2 RFD Receive FIFO Depth Configures the depth of the Rx FIFO 0 Four bytes 1 One byte The FIFO acts as a 1 byte buffer to emulate the 8250A UART 1 LM LAN Mode Enables the UART to recognize and or match an address using the 9 bit MCS 51 asynchronous protocol 0 Normal Mode 1 µLAN Mode See the ACTRL0 Register for a complete ...

Page 380: ...isters are used see Section 20 3 2 10 Table 20 57 ACTRL1 Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD D7 D6 D5 D4 D3 D3 D1 D0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R RW RW RW RW RW RW RW RW ADDR 0xFFFC2000 0x14 Table 20 58 ACTRL1 Register D...

Page 381: ...W RW RO ADDR 0xFFFC2000 0x18 Table 20 60 RIE Register Definitions BITS NAME DESCRIPTION 31 8 Reserved Do not modify Read as zero 7 CRE Control LAN Address Character Recognition Interrupt Enable 1 Enables an interrupt when the CRF bit of the RST Register is set 6 PCRE Programmable Control Address Character Match Interrupt Enable 1 Enables an interrupt on the PCRF bit of the RST Register 5 BKTE Brea...

Page 382: ...of RST Register and writes it to the Rx FIFO 01 Semi automatic Mode Same as Manual Mode but the receiver opens unlocks the Rx FIFO upon reception of any address characters Subsequent received characters are written into the FIFO You must lock the FIFO if the address character does not match the station s address 10 Automatic Mode The receiver opens unlocks the Rx FIFO upon address match Also the r...

Page 383: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RXCS TXCS RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R RW R RW R R R R ADDR 0xFFFC2000 0x00 Table 20 64 CLCF Register Definitions BITS NAME DESCRIPTION 31 7 Reserved Do not modify Read as zero 6 TXCS Transmitter Clock Source Selects the source of the internal transmit clock...

Page 384: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD BAM RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 RW R R R R R R R R R R R R R RW R R ADDR 0xFFFC2000 0x04 Table 20 66 BACF Register Definitions BITS NAME DESCRIPTION 31 3 Reserved Do not modify Read as zero 2 BAM BRGA Mode of Operation Selects between the Timer Mode or the Baud Range Generator...

Page 385: ...r see Chapter 19 Section 19 3 1 9 Table 20 67 BBL Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD D7 D6 D5 D4 D3 D2 D1 D0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 RW R R R R R R R R RW RW RW RW RW RW RW RW ADDR 0xFFFC2000 0x00 Table 20 68 BBL Register Definitions...

Page 386: ... 9 Table 20 69 BBH Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD D7 D6 D5 D4 D3 D2 D1 D0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R RW RW RW RW RW RW RW RW ADDR 0xFFFC2000 0x04 Table 20 70 BBH Register Definitions BITS NAME DESCRIPTION 31 8 Res...

Page 387: ... 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD BBCS1 BBCS0 BBM RESET 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 RW R R R R R R R R RW RW R R RO RW R R ADDR 0xFFFC2000 0x0C Table 20 72 BBCF Register Definitions BITS NAME DESCRIPTION 31 8 Reserved Do not modify Read as zero 7 6 BBCS1 BBCS0 Defines the input clock sources for BRGV 00 System clock 01 Reserved 10 BRGA outp...

Page 388: ...27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD TBIE TAIE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R RW RW ADDR 0xFFFC2000 0x18 Table 20 74 TMIE Register Definitions BITS NAME DESCRIPTION 31 3 Reserved Do not modify Read as zero 2 TBIE Timer A Expired Interru...

Page 389: ... A CPU service operation such as reading the appropriate Status Register resets the status bits 20 3 3 1 Acknowledge Modes The interrupt logic asserts an interrupt signal to the VIC when an interrupt is coded into the General Interrupt Register UART2 has two Interrupt Acknowledgment Modes Automatic Acknowledge and Manual Acknowledge An interrupt service operation is considered an automatic acknowl...

Page 390: ... line to the interrupt logic Masking off the particular block interrupt request in General Status Register via the General Enable Register This method achieves the same effect as the Enable Register method above Issuing the Status Clear command from the Internal Command Register This method is applicable to all sources Table 20 75 lists the detailed service requirements for each source Table 20 75...

Page 391: ...D HIGHEST PRIORITY TIMER TIMER B EXPIRED TRANSMITTER ERROR RX PARITY ERROR TX CONDITION RX FIFO TX FIFO LOWEST PRIORITY OVERRUN ERROR BREAK DETECTED BREAK TERMINATED FRAMING ERROR ADDRESS CONTROL CHARACTER RECEIVED ADDRESS CONTROL CHARACTER MATCH RX FIFO LEVEL ABOVE THRESHOLD TX FIFO LEVEL EQUAL TO OR BELOW THRESHOLD RX CONDITION INTERRUPT ...

Page 392: ...ut Figure 21 1 shows a block diagram of the GPIO NOTE Users may want to consult the truth tables in Chapter 24 while reading about the I O system Figure 21 1 GPIO Block Diagram LH754xx 29 PORT A REGISTERS PORT A PORT B PORT C PORT D PORT E PORT F PORT G PORT H PORT I PORT J PORT B REGISTERS PORT C REGISTERS PORT D REGISTERS APB INTERFACE PORT E REGISTERS PORT F REGISTERS PORT G REGISTERS PORT H RE...

Page 393: ... downs that can be switched on or off under software control 21 2 GPIO Theory of Operation There are 10 GPIO ports Seven 8 bit ports Two 7 bit ports One 6 bit port GPIO ports are designated A through J Pins of all ports except Port J can be configured as either inputs or outputs Port J is input only Upon System Reset all ports default to inputs Table 21 1 GPIO Ports PORT PROGRAMMABLE PINS A 8 Inpu...

Page 394: ...PGDR 0x00 RW 0x00000000 Port G Data Register PHDR 0x04 RW 0x00000000 Port H Data Register PGDDR 0x08 RW 0x00000000 Port G Data Direction Register PHDDR 0x0C RW 0x00000000 Port H Data Direction Register PEDR 0x00 RW 0x00000000 Port E Data Register PFDR 0x04 RW 0x00000000 Port F Data Register PEDDR 0x08 RW 0x00000000 Port E Data Direction Register PFDDR 0x0C RW 0x00000000 Port F Data Direction Regis...

Page 395: ...e corresponding port input if the bit is configured as an input A System Reset clears all bits Table 21 3 PADR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD Port A Data RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R RW RW RW RW RW RW RW RW ADDR 0xF...

Page 396: ...port input if the bit is configured as an input A System Reset clears all bits Table 21 5 PBDR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD Port B Data RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R RW RW RW RW RW RW ADDR 0xFFFDF000 0x04 Table...

Page 397: ...control pin 6 when the pin is configured as D11 Bit 2 controls pin 7 when the pin is configured as PA2 It does not control pin 7 when the pin is configured as D10 Bit 1 controls pin 9 when the pin is configured as PA1 it does not control pin 9 when the pin is configured as D9 Bit 0 controls pin 10 when the pin is configured as PA0 It does not control pin 10 when the pin is configured as D8 Clearin...

Page 398: ... not control pin 28 when the pin is configured as nCS3 Bit 1 controls pin 29 when the pin is configured as PB1 It does not control pin 29 when the pin is configured as nCS2 Bit 0 controls pin 30 when the pin is configured as PB0 It does not control pin 30 when the pin is configured as nCS1 Clearing a bit configures the pin to be an input A System Reset clears all bits Table 21 9 PBDDR Register BIT...

Page 399: ...rt input if the bit is configured as an input A System Reset clears all bits Table 21 11 PCDR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD Port C Data RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R RW RW RW RW RW RW RW RW ADDR 0xFFFDE000 0x00 Tabl...

Page 400: ...ort input if the bit is configured as an input A System Reset clears all bits Table 21 13 PDDR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD Port D Data RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R RW RW RW RW RW RW RW ADDR 0xFFFDE000 0x04 Tabl...

Page 401: ...ot control pin 37 when the pin is configured as A19 Bit 2 controls pin 38 when the pin is configured as PC2 It does not control pin 38 when the pin is configured as A18 Bit 1 controls pin 39 when the pin is configured as PC1 It does not control pin 39 when the pin is configured as A17 Bit 0 controls pin 40 when the pin is configured as PC0 It does not control pin 40 when the pin is configured as A...

Page 402: ... UARTTX1 Bit 2 controls pin 77 when the pin is configured as PD2 It does not control pin 77 when the pin is configured as INT2 Bit 1 controls pin 78 when the pin is configured as PD1 It does not control pin 78 when the pin is configured as INT1 Bit 0 controls pin 79 when the pin is configured as PD0 It does not control pin 79 when the pin is configured as INT0 Clearing a bit configures the pin to ...

Page 403: ...ort input if the bit is configured as an input A System Reset clears all bits Table 21 19 PEDR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD Port E Data RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R RW RW RW RW RW RW RW RW ADDR 0xFFFDD000 0x00 Tab...

Page 404: ...e corresponding port input if the bit is configured as an input A System Reset clears all bits Table 21 21 PFDR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD Port F Data RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R RW RW RW RW RW RW RW ADDR 0xF...

Page 405: ...TTX0 Bit 2 controls pin 104 when the pin is configured as PE2 It does not control pin 104 when the pin is configured as CANRX or UARTRX0 Bit 1 controls pin 105 when the pin is configured as PE1 It does not control pin 105 when the pin is configured as UARTTX2 Bit 0 controls pin 107 when the pin is configured as PE0 It does not control pin 106 when the pin is configured as UARTRX2 Clearing a bit co...

Page 406: ...A or CTCMP1A Bit 2 controls pin 113 when the pin is configured as PF2 It does not control pin 113 when the pin is configured as CTCAP0E Bit 1 controls pin 114 when the pin is configured as PF1 It does not control pin 114 when the pin is configured as CTCAP0D Bit 0 controls pin 115 when the pin is configured as PF0 it does not control pin 115 when the pin is configured as CTCAP0C Clearing a bit con...

Page 407: ... input if the bit is configured as an input A System Reset clears all bits Table 21 27 PGDR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD Port G Data RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R RW RW RW RW RW RW RW RW ADDR 0xFFFDC000 0x00 Table ...

Page 408: ...f the bit is configured as an input A System Reset clears all bits Table 21 29 PHDR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD Port H Data RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R RW RW RW RW RW RW RW RW ADDR 0xFFFDC000 0x04 Table 21 30 PH...

Page 409: ...d as LCDVDDEN Bit 2 controls pin 122 when the pin is configured as PG2 It does not control pin 122 when the pin is configured as LCDDSPLEN or LCDREV Bit 1 controls pin 123 when the pin is configured as PG1 It does not control pin 123 when the pin is configured as LCDCLS Bit 0 controls pin 124 when the pin is configured as PG0 It does not control pin 124 when the pin is configured as LCDPS Clearing...

Page 410: ...in 132 when the pin is configured as PH2 It does not control pin 132 when the pin is configured as LCDVD10 Bit 1 controls pin 133 when the pin is configured as PH1 It does not control pin 133 when the pin is configured as LCDVD9 Bit 0 controls pin 135 when the pin is configured as PH0 It does not control pin 135 when the pin is configured as LCDVD8 Clearing a bit configures the pin to be an input ...

Page 411: ...r returns either The last bit value written if the bit is configured as an output The current value on the corresponding port input if the bit is configured as an input A System Reset clears all bits Table 21 35 PIDR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F...

Page 412: ...bits Table 21 37 PJDR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD Port J Data RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R RW RW RW RW RW RW RW RW ADDR 0xFFFDB000 0x04 Table 21 38 PJDR Register Definitions BITS NAME FUNCTION 31 8 Reserved Writi...

Page 413: ... configured as LCDVD3 Bit 2 controls pin 142 when the pin is configured as PI2 It does not configure pin 142 when the pin is configured as LCDVD2 Bit 1 controls pin 143 when the pin is configured as PI1 It does not configure pin 143 when the pin is configured as LCDVD1 Bit 0 controls pin 144 when the pin is configured as PI0 It does not control pin 144 when the pin is configured as LCDVD0 Clearing...

Page 414: ...ler and the CAN bus All peripherals share the TX and RX lines and always see the common incoming and outgoing data Data to be transmitted by the CAN Controller is placed in the Transmit Buffer and passed to the Bit Processor which channels the data onto the TX signal Messages received by the CAN Controller are filtered by the Acceptance Filter and placed in a 64 byte Receive FIFO The 64 byte Recei...

Page 415: ...nerated for each CAN bus error Arbitration lost interrupt with record of bit position Read write error counters Last error register Programmable error limit warning 22 2 CAN Theory of Operation The CAN Controller has two operating modes Operating Mode during which data can be transmitted and received Reset Mode in which special modes of operation such as changing the values for the Receive and Tra...

Page 416: ...ices 22 2 2 Frame Types The data received and transmitted on a CAN interface are referred to as frames CAN uses four types of frames each with its own format The message frame contains data The remote frame requests data from the network The error frame reports errors that occurred at a node The overload frame delays transmission of a CAN frame if the receive node is not ready 22 2 2 1 Message Fra...

Page 417: ...ending a message frame Since errors can occur when data is being transmitted or received the CAN Controller can track these errors and generate an interrupt based on a predetermined value This type of constant checking for potential errors makes the CAN bus extremely desirable in any elec trically hostile environment 22 2 3 Transmitted and Received Data Data transmitted to the CAN Controller can f...

Page 418: ...portant The CAN standard allows bit timing to be organized into four segments to allow for synchronization A synchronization segment The propagation segment Phase segment 1 Phase segment 2 These segments can be organized into time blocks called time quantum The time quantum specifies how often the bit timing is sampled to ensure that data is correct The time quantum is defined as a fixed amount of...

Page 419: ...ered According to the CAN protocol once the error count exceeds 255 the bus must be released and the network stopped This status is reflected in the Status Register If the error count exceeds 127 the CAN Controller enters an Error Passive state as defined in the CAN protocol The Error Warning Limit Register defaults to 96 decimal if either counter exceeds this value the Error Status bit in the Sta...

Page 420: ...Bus Timing 1 Register 0x00 0x20 Reserved 0x24 Reserved 0x28 Reserved returns 00h when read ALC 0x02C R R Arbitration Lost Capture Register 0x00 ECC 0x30 R R Error Code Capture Register 0x00 EWLR 0x34 R RW Error Warning Limit Register 0x60 RXERR 0x38 R RW Receive Error Counter Register 0x00 TXERR 0x3C R RW Transmit Error Counter Register 0x00 Transmit Buffer 0x40 W RW Transmit Frame Information Reg...

Page 421: ...served Writing to these bits has no effect Reading returns 0 4 Reserved Do not modify Read as 0 3 AFM Acceptance Filter Mode 0 Dual filter Receive data is filtered using two shorter filters 1 Single filter Receive data is filtered using one 4 byte filter 2 STM Self Test Mode 0 Normal operation An acknowledge is required for successful transmission 1 Enable Self Test Mode In this mode a full node t...

Page 422: ...egister BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD SRR CDO RRB AT TR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R W W W W W ADDR 0xFFFC5000 0x04 Table 22 5 CMR Register Definitions BIT NAME DESCRIPTION 31 5 Reserved Writing to these bits has no e...

Page 423: ...ransmit Status bits are 0 the CAN bus is idle If both bits are 1 the CAN Controller is waiting to become idle again After a System Reset Idle state is entered once the Bus Free sequence 11 consecutive recessive bits is detected After a Bus Off event 128 Bus Free sequences must be received before Idle state is entered For bit 1 the overrun condition is only indicated if the entire message was recei...

Page 424: ...tus 0 Last requested transmission has not completed 1 Last requested transmission has successfully completed 2 TBS Transmit Buffer Status 0 Transmit buffer locked The CPU cannot access the transmit buffer because a message is either waiting for transmission or is being transmitted 1 Transmit buffer released The CPU may write a message to the transmit buffer 1 DOS Data Overrun Status 0 No data over...

Page 425: ...ve state or when at least one error counter exceeds the protocol defined level of 127 provided bit 5 of the Interrupt Enable Register is set see Section 22 3 2 5 4 WUI Wake Up Interrupt 1 Bus activity is detected provided bit 4 of the Interrupt Enable Register is set see Section 22 3 2 5 A wake up interrupt is also generated if the CPU tries to set bit 4 of the MOD Register while the CAN Controlle...

Page 426: ... interrupt is generated when the CAN Controller loses arbitration 5 EPIE Error Passive Interrupt Enable 0 Interrupt is disabled 1 An interrupt is generated when the error status of the CAN Controller changes from error active to error passive or vice versa 4 Reserved 3 DOIE Data Overrun Interrupt Enable 0 Interrupt is disabled 1 An interrupt is generated when bit 1 of the Status Register is set se...

Page 427: ... BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFC5000 0x18 Table 22 13 BTR0 Register Definitions BITS NAME DESCRIPTION 31 8 Reserved Writing to these bits has no effect Reading returns 0 7 6 SJW Synchronization Jump Width Defines the maximum number of clock cycles by which a bit period can be shortened or lengthened in attempt ing t...

Page 428: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFC5000 0x1C Table 22 15 BTR1 Register Definitions BITS NAME DESCRIPTION 31 8 Reserved Writing to these bits has no effect Reading returns 0 7 SAM Sampling 0 Bus will be sampled once This is recommended for high speed bus es SAE class C 1 Bus will be sampled three times This is recommended for low and medium speed buses clas...

Page 429: ...are Then the capture mechanism is activated again The Arbitration Lost Capture Register appears to the CPU as Read Only memory The Reserved bits always return 0 Table 22 16 ALC Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD Arbitration Loss RESET 0 0 0 0 0 0 ...

Page 430: ...ost in IDE bit 0 1 1 0 1 13 Arbitration lost in 12th bit of identifier ID 17 2 0 1 1 1 0 14 Arbitration lost in 13th bit of identifier ID 16 2 0 1 1 1 1 15 Arbitration lost in 14th bit of identifier ID 15 2 1 0 0 0 0 16 Arbitration lost in 15th bit of identifier ID 14 2 1 0 0 0 1 17 Arbitration lost in 16th bit of identifier ID 13 2 1 0 0 1 0 18 Arbitration lost in 17th bit of identifier ID 12 2 1...

Page 431: ...ory Table 22 19 ECC Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD Error Code Direction Segment Code RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R ADDR 0xFFFC5000 0x30 Table 22 20 ECC Register Definitions BIT NAME DESCRIPTION 31 8 Reserved Wr...

Page 432: ...D 17 to ID 13 0 1 1 1 1 ID 12 to ID 5 0 1 1 1 0 ID 4 to ID 0 0 1 1 0 0 RTR bit 0 1 1 0 1 Reserved bit 1 0 1 0 0 1 Reserved bit 0 0 1 0 1 1 Data Length code 0 1 0 1 0 Data field 0 1 0 0 0 CRC sequence 1 1 0 0 0 CRC delimiter 1 1 0 0 1 Acknowledge 1 1 0 1 1 Acknowledge delimiter 1 1 0 1 0 End of frame 1 0 0 1 0 Intermission 1 0 0 0 1 Active error flag 1 0 1 1 0 Passive error flag 1 0 0 1 1 Tolerate ...

Page 433: ... value of this register after System Reset is 0110000 i e 96 Table 22 23 EWLR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD EWL 7 EWL 6 EWL 5 EWL 4 EWL 3 EWL 2 EWL 1 EWL 0 RESET 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFC50...

Page 434: ...to effect when the CAN Controller returns to Operating Mode In Operating Mode this register is Read Only Writing to this register has no effect when the CAN Controller is in Bus Off state Table 22 25 RXERR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RXERR ...

Page 435: ...y memory While in Bus Off state writing a value in the range from 0 to 254 to the TXERR Register clears the Bus Off flag The CAN Controller then waits one Bus Free sequence after the Reset Mode clears Writing 255 to the TXERR Register initiates a CPU driven bus off event Note that a CPU forced content change of the transmit error counter is only possible if Reset Mode was entered previously An err...

Page 436: ...by either two identifier bytes for SFF messages or four bytes for EFF messages The data field contains up to eight data bytes NOTE Direct read only access to the Transmit Buffer is possible using the CAN offset space from 0x180 to 0x1B0 Table 22 27 CAN Transmit Buffer STANDARD FRAME FORMAT EXTENDED FRAME FORMAT CAN OFFSET FIELD CAN OFFSET FIELD 0x40 TX Frame Information 0x40 TX Frame Information 0...

Page 437: ...ut 0 is recommended for compatibility with the Receive Buffer in case the Self Reception or the Self Test option is used 2 Don t care but matching the RTR bit in the Receive Buffer is recommended in case the Self Reception or the Self Test option is used Table 22 28 Transmit Frame SFF CAN OFFSET BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0X40 FF RTR x1 x1 DLC 3 DLC 2 DLC 1 DLC 0 0X44 ID 28 ID...

Page 438: ...ly Consult the CAN 2 0B specification for a complete description about data length encoding Note too that although no data bytes are transmitted from the local host in the case of a remote frame transmission the data length of the re mote frame should still be specified to avoid bus errors if two CAN Controllers start a remote frame transmission with the same identifier simultaneously ID Identifie...

Page 439: ...ame information It describes the frame format SFF or EFF specifies remote or data frame and gives the data length This is then followed by either two identifier bytes for SFF messages or four bytes for EFF messages The data field contains up to eight data bytes Table 22 31 CAN Receive Buffer STANDARD FRAME FORMAT EXTENDED FRAME FORMAT CAN OFFSET FIELD CAN OFFSET FIELD 0x40 RX Frame Information 0x4...

Page 440: ... in Reset Mode 22 3 2 18 Acceptance Mask Registers AMR0 AMR3 Registers AMR0 AMR1 AMR2 and AMR3 are the Acceptance Mask Registers These 8 bit registers record the mask patterns applied by the Acceptance Filter when filtering received data Register values of zero identify the bits of the incoming data bytes that are required to match the bit values in the corresponding Acceptance Code Registers Regi...

Page 441: ...The register is reset to 00h by either a System Reset or a Software Reset Table 22 34 RMC Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD RMC 4 RMC 3 RMC 2 RMC 1 RMC 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFC5000 0x7...

Page 442: ...ware Reset to the value of the RX FIFO Read Pointer As a result the data accessed by the Receive Buffer following a Software Reset is overwritten by the next mes sage to be recorded in the RX FIFO NOTE It is only possible to write to this register in Reset Mode Table 22 36 RBSA Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R...

Page 443: ... to Bus Off Table 22 38 describes the effect of the reset on the CAN Controller registers In this table x means the reset has no effect on the value of these registers or bits Table 22 38 Effect of Reset on CAN Controller Registers REGISTER BIT SYMBOL NAME RESET VALUE NOTES SYSTEM SOFTWARE Mode 7 5 Reserved 0 reserved 0 reserved 4 Reserved 0 reserved 0 reserved 3 AFM Acceptance Filter Mode 0 dual ...

Page 444: ...Bus Timing 0 7 SJW 1 Synchronization Jump Width 1 0 x 6 SJW 0 Synchronization Jump Width 0 0 x 5 BRP 5 Bit Rate Prescaler 5 0 x 4 BRP 4 Bit Rate Prescaler 4 0 x 3 BRP 3 Bit Rate Prescaler 3 0 x 2 BRP 2 Bit Rate Prescaler 2 0 x 1 BRP 1 Bit Rate Prescaler 1 0 x 0 BRP 0 Bit Rate Prescaler 0 0 x Bus Timing 1 7 SAM Sampling 0 x 6 TSEG2 2 Time Segment 2 2 0 x 5 TSEG2 1 Time Segment 2 1 0 x 4 TSEG2 0 Tim...

Page 445: ...MR0 through AMR3 identifies the bits at the corresponding positions in ACR0 through ACR3 which must be matched in the message identifier A value 1 identifies the corresponding bits as don t care The bit patterns recorded in the ACR0 ACR3 Registers can be used as either a single 4 byte filter or as two shorter filters The selection is made through the AFM bit bit 3 of the Mode Register see Section ...

Page 446: ...t Dual Filters Receive Buffer and Filters DATA WITH OFFSET 0x44 0x48 0x4C 0x50 ID 28 ID 21 ID 20 ID18 RTR x x x x not matched Data Byte 1 7 4 Data Byte 1 3 0 Data Byte 2 not matched DUAL FILTERS FILTER 1 ACR0 7 0 ACR1 7 4 ACR1 3 0 ACR3 3 0 AMR0 7 0 AMR1 7 4 AMR1 3 0 AMR3 3 0 DUAL FILTERS FILTER 2 ACR2 7 0 ACR3 7 4 AMR2 7 0 AMR3 7 4 Table 22 41 Extended Frame Format Single Filter Receive Buffer and...

Page 447: ...g to digital conversion reference generation and digital control The ADC has a bias and control network that allows correct operation with both 4 and 5 wire touch panels A 16 entry 16 bit wide FIFO holds a 10 bit ADC output and a 4 bit tag number When the screen is touched it pushes the conductive coating on the cover sheet against the coating on the glass making electrical contact The voltages pr...

Page 448: ... AN3 LR Y AN2 LL Y AN1 UR X AN0 UL X AN6 VBAT A2DCLK DIGITAL EOSINTR A2DCLK ANALOG Start_acq A2DON PWM penIRQ EOC A2DCLK DIGITA HWR LWR CBTAG 4 TO 1 MUX AN8 VREF EXT AN0 UL X VLL GPI MUX BrownOut_INTR VREF LL Y VREF A2DCLK_ANALOG REF IN D 9 0 START A2DON REF 10b A D OUT IN 4 TO 1 MUX FIFO 10 BIT RESULT CBTAG XX BGAP VREF VREF EN VREF CBTAG FwaterINTR FovmINTR ADVANCED PERIPHERAL BUS APB VREF EXT A...

Page 449: ... Interrupt Masking Enabling Register see Section 23 3 2 4 In 5 wire operation panel connections are to UL UR LL and LR inputs and the sense input is connected to WIPER The Pen Interrupt line is also available in this mode NOTE For pen triggered interrupts use the following procedure instead of using the WIPER s Pen Interrupt PENIRQ pull up Before checking the Pen Down state use bias and control ne...

Page 450: ...rrupt the processor core This allows the Host Controller to warn users of an impending shutdown and may provide the ADC with time to save its state For Brownout Detector trip point and hysteresis levels see Chapter 24 NOTE The Brownout Detector indicates a brownout condition on startup until the VDDA pin rises above the trip point Figure 23 2 Bias and Control Network Block Diagram LH754xx 28 11 TO...

Page 451: ...hether VIN is less than or greater than VDAC If VIN is less than VDAC the comparator output is a logic LOW and the most significant bit of the N bit register is cleared to 0 If VIN is greater than VDAC the comparator output is a logic HIGH or 1 and the most significant bit of the N bit register remains set to 1 The SAR control logic then moves to the next bit down forces that bit HIGH and conducts...

Page 452: ...e last comparison 4 In the final comparison bit 0 remains at 1 because VIN VDAC Four comparison periods are necessary for a 4 bit ADC Generally an N bit SAR ADC requires N comparison periods and will not be ready for the next conversion until the cur rent conversion is completed This explains why the ADC is power and space efficient Another feature of SAR ADCs is that power dissipation scales with...

Page 453: ...ry from the control bank and stores it in the registers LW and HW for the duration of the measurement When the measurement is complete the control bank state machine Stores the ADC result and the control bank instruction number in the measurement FIFO Obtains the next configuration from the control bank into LW and HW When all steps of the sequence are complete or at a programmed FIFO watermark le...

Page 454: ...0000 Results Register IM 0x0C RW 0x0000 Interrupt Masking Register PC 0x10 RW 0x0000 Power Configuration Register GC 0x14 RW 0x0000 General Configuration Register GS 0x18 R 0x0210 General Status Register IS 0x1C R 0x0010 Interrupt Status Register FS 0x20 R 0x0004 FIFO Status Register HWCB0 HWCB15 0x24 0x60 RW 0x0000 High Word Control Bank Registers LWCB0 LWCB15 0x64 0xA0 RW 0x0000 Low Word Control...

Page 455: ...R R R R R R R R R R R ADDR 0xFFFC3000 0x00 Table 23 3 HW Register Definitions BITS NAME DESCRIPTION 31 16 Reserved Read as zero 15 7 SETTIME Number of Clock Cycles Number of clock cycles that the ADC allows for the input signal to settle to within required accuracy before beginning conversion Used with bits 10 8 of the PC Register to set the acquire time in clock cycles see Section 23 3 2 5 For ex...

Page 456: ... 6 25 03 Table 23 4 In Mux Definition IN BIT6 BIT5 BIT4 BIT3 AN0 UL X 0 0 0 0 AN1 UR X 0 0 0 1 AN2 LL Y 0 0 1 0 AN3 LR Y 0 0 1 1 AN4 Wiper 0 1 0 0 RESERVED 0 1 0 1 AN6 0 1 1 0 RESERVED 0 1 1 1 AN8 1 0 0 0 AN9 1 0 0 1 VREF 1 0 1 0 VREF 1 0 1 1 VREF 1 1 0 0 VREF 1 1 0 1 VREF 1 1 1 0 VREF 1 1 1 1 ...

Page 457: ...24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD BIASCON RefM RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFC3000 0x04 Table 23 6 LW Register Definitions BIT NAME DESCRIPTION 31 14 Reserved Read as zero 13 2 BIASCON Bias Control These bits drive the FETs as ...

Page 458: ...moves an entry from the First Out end of the result FIFO Table 23 7 RR Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD BITRES CBTAG RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFC3000 0x08 Table 23 8 RR Register Definitions...

Page 459: ... 9 IM Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD INTEN BOMSK PMSK EOSMSK FWMSK FOMSK RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R RW R RW RW RW RW RW ADDR 0xFFFC3000 0x0C Table 23 10 IM Register Definitions BIT NAME DESCRIPTION 31 7 Reserved...

Page 460: ...able 23 11 PC Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD CLKSEL PWM REFEN NOC RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R RW RW RW RW RW RW RW RW RW RW R RW RW RW RW ADDR 0xFFFC3000 0x10 Table 23 12 PC Register Definitions BIT NAME DESCRIPTION 31 15 Reserv...

Page 461: ...f Power Mode and clock sets the BROWNOUT field bit 9 of the GS Register indicating that a brownout is detected even if VDDA_ADC is at the correct voltage 01 Standby wake on SSB or Pen Interrupt convert return clears the BROWNOUT field bit 9 of the GS Register even if VDDA_ADC is at the correct voltage 10 Run always on clears the BROWNOUT field bit 9 of the GS Register even if VDDA_ADC is at the co...

Page 462: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD FIFOWMK SSB SSM RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R RW RW RW RW RW RW RW ADDR 0xFFFC3000 0x14 Table 23 15 GC Register Definitions BIT NAME DESCRIPTION 31 7 Reserved Read as zero 6 3 FIFOWMK FIFO Watermark Programmed to values between 0 and 15 This value cor respond...

Page 463: ...scharge any charge stored in debounce capacitors 7 Configure for Pen Down detect a Set the NOC bits bits 3 0 of the PC Register to 1 two measurements and set the SSM bits of this register for pen triggered measurements b Set up a Pen Interrupt handler that changes the SSM field to SSB triggered mea surements This prevents Pen Down from retriggering additional measurements c Set up an End of Sequen...

Page 464: ...nd then stops the timer Next install an end of sequence interrupt handler that reads the measurement results and deter mines whether the pen is still down If the pen is down the handler starts the timer for triggering the next measurement The handler discards the first set of measurements taken during the initial Pen Down detection Otherwise the handler posts the current pen position to some sort ...

Page 465: ... 0 0 0 0 0 0 0 0 0 1 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFC3000 0x1C Table 23 19 IS Register Definitions BIT NAME DESCRIPTION 31 5 Reserved Read as zero 4 BROWNOUTINTR_UM Brown Out Interrupt Status 0 Brown out Interrupt is not active 1 Brown out Interrupt is active 3 PENSYNC_UM Pen Interrupt Status 0 Pen Interrupt is not active 1 Pen Interrupt is active 2 EOSINTR_UM End of Sequence...

Page 466: ... Current FIFO location where the write pointer is pointing 7 4 RSPTR Read Pointer FIFO Location Current FIFO location where the read pointer is pointing 3 FFF FIFO Full 0 FIFO is not full 1 FIFO is full 2 FEMPTY FIFO Empty 0 FIFO is not empty 1 FIFO is empty 1 FOVRNDET FIFO Overrun Status Bit Set when the receive logic tries to place data into the FIFO after it has been completely filled When a ne...

Page 467: ... the low words are read as zero The same logic is used for the Control Bank Registers HWCBx and LWCBx The High Word Registers should contain the Settling time In bits In bits Ref bits The Low Word Registers should contain the Bias control settings Ref bits For internal access into the control bank the data writes to the registers from the APB data bus Each entry is a 16 bit register with its own a...

Page 468: ..._ID REFP_ID RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC3000 0xA4 Table 23 24 IHWCTRL Register Definitions BIT NAME DESCRIPTION 31 16 Reserved Read as zero 15 7 SETTIME_ID Idle Settling Time Specifies the delay in ADC clock cycles from when the state machine enters the Idle state to when the Pen Interrupt signal can be activated Prevents spur...

Page 469: ...er BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD BIASCON_ID REFM_ID RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW ADDR 0xFFFC3000 0xA8 Table 23 26 ILWCTRL Register Definitions BIT NAME DESCRIPTION 31 14 Reserved Read as zero 1...

Page 470: ...T 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R R R R R R ADDR 0xFFFC3000 0xAC Table 23 28 MIS Register Definitions BIT NAME DESCRIPTION 31 5 Reserved Read as zero 4 BROWNOUT Brown Out Interrupt Status 0 Brown out Interrupt is not active 1 Brown out Interrupt is active 3 PENSYNC Pen Interrupt Status 0 Pen Interrupt is not active 1 Pen Interrupt is active 2 EOSINTR End of Sequence Interr...

Page 471: ...ts one cycle of the system clock NOTE The reset value of this register s bits is indeterminate Table 23 29 IC Register BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIELD RESET RW W W W W W W W W W W W W W W W W BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD BOIC PENIC EOSINTC RESET RW W W W W W W W W W W W W W W W W ADDR 0xFFFC3000 0xB0 Table 23 30 IC Register Definitions BITS NAME DESCRIP...

Page 472: ... cycle in the End of Sequence state This equals Two cycles plus The number of measurements in sequence times plus The throughput conversion time 17 cycles plus The number of settling time cycles per measurement 23 3 4 ADC Interrupts The ADC has five interrupts Brownout Interrupt BrownOutINTR Pen Interrupt PenIRQ End of Sequence Interrupt FIFO Watermark Interrupt FIFO Overrun Interrupt All five int...

Page 473: ...he latched value of the Pen Interrupt that s stored in the Interrupt Status Register The raw status of the Pen Interrupt is stored in the GS Register see Section 23 3 2 8 The Pen Interrupt has its own dedicated output NOTES 1 If a measurement sequence is configured to keep the Touch Screen biased for Pen detect on every mea surement PENIRQ is not generated on every sequence If on the other hand th...

Page 474: ... FIFO after the FIFO has been completely filled exceeding the FIFO s maximum capacity of 16 entries The interrupt is cleared when the FIFO is read Figure 23 5 Bias and Control Network Block Diagram LH754xx 28 11 TO 1 ANALOG MUX A D IN B12 PENIRQ B8 B7 B6 B4 B2 AVDD AVDD AVDD AVDD AN0 UL X B3 AN1 UR X B5 AN2 LL Y AN6 A3 TSCHWR 6 A2 TSCHWR 5 A1 TSCHWR 4 A0 TSCHWR 3 AN8 AN9 AN3 LR Y AN4 WIPER VREF B1...

Page 475: ...ver pin NOTES 1 MUSTN Mono upper panel STN dual and or single panel 2 MLSTN Mono lower panel STN dual Table 24 1 LCD Panel Signal Multiplexing EXTERNAL PIN 4 BIT MONO STN 8 BIT MONO STN SINGLE PANEL SINGLE PANEL DUAL PANEL LVCVD 11 Reserved MLSTN 3 Reserved LVCVD 10 Reserved MLSTN 2 Reserved LVCVD 9 Reserved MLSTN 1 Reserved LVCVD 8 Reserved MLSTN 0 Reserved LVCVD 7 Reserved Reserved MUSTN 7 LVCVD...

Page 476: ...PH7 LCDDCLK LCDDCLK LCDDCLK LCDDCLK LCDDCLK PH6 LCDLP LCDHRLP PH6 LCDLP LCDLP LCDLP LCDLP LCDLP PH5 LCDFP LCDSPS PH5 LCDFP LCDFP LCDFP LCDFP LCDFP PH4 LCDEN LCDEN PH4 LCDEN LCDEN LCDEN LCDEN LCDEN PH3 LCDVD11 PH3 PH3 MLSTN3 PH3 LCDVD11 LCDVD11 PH2 LCDVD10 PH2 PH2 MLSTN2 PH2 LCDVD10 LCDVD10 PH1 LCDVD9 PH1 PH1 MLSTN1 PH1 LCDVD9 LCDVD9 PH0 LCDVD8 PH0 PH0 MLSTN0 PH0 LCDVD8 LCDVD8 PI7 LCDVD7 PI7 PI7 PI...

Page 477: ...DSPLEN PG1 PG1 PG1 PG1 PG1 PG0 PG0 PG0 PG0 PG0 PH7 LCDDCLK PH7 LCDDCLK LCDDCLK LCDDCLK PH6 LCDLP PH6 LCDLP LCDLP LCDLP PH5 LCDFP PH5 LCDFP LCDFP LCDFP PH4 LCDEN PH4 LCDEN LCDEN LCDEN PH3 LCDVD11 PH3 PH3 MLSTN3 PH3 PH2 LCDVD10 PH2 PH2 MLSTN2 PH2 PH1 LCDVD9 PH1 PH1 MLSTN1 PH1 PH0 LCDVD8 PH0 PH0 MLSTN0 PH0 PI7 LCDVD7 PI7 PI7 PI7 STN7 PI6 LCDVD6 PI6 PI6 PI6 STN6 PI5 LCDVD5 PI5 PI5 PI5 STN5 PI4 LCDVD4 ...

Page 478: ...ag Handle an LH75400 01 10 11 board by the edges only avoid touching the components traces or any connector pins 25 1 1 Special ESD Considerations A typical application for the Analog to Digital converter in the LH75400 01 10 11 devices is interfacing to a Touch Screen panel Normally this application requires filtering on the inputs and can be subject to ESD from users It is recommended that ESD d...

Page 479: ...lk 10 µF capacitor for each power supply placed near one side of the chip 25 2 2 Required VDDA_PLL VSSA_PLL Filter The VDDA_PLL pin supplies power to the chip PLL circuitry VSSA_PLL is the ground return path for the PLL circuit If the internal PLL circuit will be used these pins must have a low pass filter attached as shown in Figure 25 1 The power pin VDDA_PLL path must be a single wire from the ...

Page 480: ...s at reset see Chapter 1 Section 1 8 25 2 4 Other Circuit Board Layout Practices All output pins have fast rise and fall times Printed circuit trace interconnection length must therefore be reduced to minimize overshoot undershoot and reflections caused by transmission line effects of these fast output switching times This recommendation partic ularly applies to the address and data buses When con...

Page 481: ...OW on Reset Bank0 defaults to an 8 bit memory width Table 26 1 SMC Register Summary NAME ADDRESS OFFSET TYPE WIDTH RESET VALUE DESCRIPTION BCR0 SMC RegBase 0x00 RW 32 0x1000FFEF 16 bit or 0x0000FBEF 8 bit Configuration Register for Memory Bank 0 BCR1 SMC RegBase 0x04 RW 32 0x1000FFEF Configuration Register for Memory Bank 1 BCR2 SMC RegBase 0x08 RW 32 0x1000FFEF Configuration Register for Memory B...

Page 482: ...et Status Register ResetStatusClr 0x14 W Reset Status Clear Register SysClkPrescaler 0x18 RW 0xF System Clock Prescaler Register 0x1C 0x20 Reserved APBPeriphClkCtrl0 0x24 RW 0x3FF Peripheral Clock Control 0 Register APBPeriphClkCtrl1 0x28 RW 0x3 Peripheral Clock Control 1 Register AhbClkCtrl 0x2C RW 0x1 AHB Clock Control 0x30 0x3C Reserved LCDPrescaler 0x40 RW 0x00 LCD Prescaler Register SSPPresca...

Page 483: ...ess 4 Register VectAddr 5 0x114 RW 0x00000000 Vector Address 5 Register VectAdd 6 0x118 RW 0x00000000 Vector Address 6 Register VectAddr 7 0x11C RW 0x00000000 Vector Address 7 Register VectAddr 8 0x120 RW 0x00000000 Vector Address 8 Register VectAddr 9 0x124 RW 0x00000000 Vector Address 9 Register VectAddr 10 0x128 RW 0x00000000 Vector Address 10 Register VectAddr 11 0x12C RW 0x00000000 Vector Add...

Page 484: ...tor Control 12 Register VectCtrl 13 0x234 RW 0x00 Vector Control 13 Register VectCtrl 14 0x238 RW 0x00 Vector Control 14 Register VectCtrl 15 0x23C RW 0x00 Vector Control 15 Register 0x300 Reserved 0x304 Reserved 0x308 Reserved 0x30C R 0x0 Reserved 0x310 Reserved Table 26 3 VIC Register Summary Cont d NAME ADDRESS OFFSET TYPE RESET VALUE DESCRIPTION ...

Page 485: ... Muxing Register LCD_MUX 0x10 RW 0x0000 LCD Mode Muxing Register PA_RES_MUX 0x14 RW 0xAAAA Pins PA7 D15 to PA0 D8 Resistor Muxing Register PB_RES_MUX 0x18 RW 0x0555 Pins PB5 nWAIT to PB0 nCS1 Resistor Muxing Register PC_RES_MUX 0x1C RW 0x0000 Pins PC7 A23 to PC0 A16 Resistor Muxing Register PD_RES_MUX 0x20 RW 0x095A Pins PD6 INT6 to PD0 INT0 Resistor Muxing Register PE_RES_MUX 0x24 RW 0x4455 Pins ...

Page 486: ...address higher 16 bits DestLo 0x008 RW Destination base address lower 16 bits DestHi 0x00C RW Destination base address higher 16 bits Max 0x010 RW Maximum Count Register Ctrl 0x014 RW Control Register SoCurrHi 0x018 R Current source address higher 16 bits SoCurrLo 0x01C R Current source address lower 16 bits DeCurrHi 0x020 R Current destination address lower 16 bits DeCurrLo 0x024 R Current destin...

Page 487: ... Base Address Register INTRENABLE 0x018 RW 0x00000000 Interrupt Enable Register Ctrl 0x01C RW 0x0000 LCD Panel Parameters LCD Panel Power and CLCDC Control Register Status 0x020 RW 0x00000000 Raw Interrupt Status Register Interrupt 0x024 R 0x00000000 Final Masked Interrupts Register UPCURR 0x028 R 0x00000000 Upper Panel Frame Buffer Current Address Register LPCURR 0x02C R 0x00000000 Lower Panel Fr...

Page 488: ...ved UPBASE 0x010 RW 0x0000000 Upper Panel Frame Buffer Base Address Register LPBASE 0x014 RW 0x00000000 Lower Panel Frame Buffer Base Address Register INTRENABLE 0x018 RW 0x00000000 Interrupt Enable Register CTRL 0x01C RW 0x0000 LCD Panel Parameters LCD Panel Power and LCDC Control Register Status 0x020 RW 0x00000000 Raw Interrupt Status Register Interrupt 0x024 R 0x00000000 Final Masked Interrupt...

Page 489: ...0 Timer 0 Capture Register 4 Table 26 11 Timer 1 Register Summary NAME ADDRESS OFFSET TYPE RESET VALUE DESCRIPTION CTRL 0x30 RW 0x0000 Timer 1 Control Register INT_CTRL 0x34 RW 0x0000 Timer 1 Interrupt Control Register STATUS 0x38 RW 0x0000 Timer 1 Status Register CNT 0x3C RW 0x0000 Timer 1 Counter Register CMP0 0x40 RW 0xFFFF Timer 1 Compare Register 0 CMP1 0x44 RW 0xFFFF Timer 1 Compare Register...

Page 490: ...T Counter Section 0 CNT1 0x10 R 0x00 WDT Counter Section 1 CNT2 0x14 R 0x01 WDT Counter Section 2 CNT3 0x18 R 0x00 WDT Counter Section 3 Table 26 14 RTC Register Summary NAME ADDRESS OFFSET TYPE RESET VALUE DESCRIPTION DR0 0x00 R Lower 16 bit Data Register DR1 0x04 R Upper 16 bit Data Register MR0 0x08 RW Lower 16 bit Match Register MR1 0x0C RW Upper 16 bit Match Register STAT EOI 0x10 RW Interrup...

Page 491: ... 0xFFF Reserved Table 26 16 UART0 and UART1 Register Summary NAME ADDRESS OFFSET TYPE RESET VALUE DESCRIPTION DR 0x000 RW 0x Data read or written from the interface It is 12 bits wide on a read and 8 on a write RSR ECR 0x004 RW 0x0 Receive Status Register read Error Clear Register write 0x008 0x014 Reserved FR 0x018 R 0x00000090 Flag Register read only 0x01C 0x020 Reserved IBRD 0x024 R 0x0000 Inte...

Page 492: ...ntrol Register MCTRL 0x10 RW 0x00 Loopback Control Register LSR 0x14 RW 0x60 Line Status Register 0x18 Reserved ACTRL0 0x1C RW 0x00 Address Control Character Register 0 Table 26 18 UART2 Register Summary Register Bank 1 NAME ADDRESS OFFSET DLAB TYPE RESET VALUE DESCRIPTION TXD 0x00 W Transmit Buffered Data Register RXD 0x00 R 0x00 Receive Buffered Data Register TXF 0x04 W Transmit Character Flag R...

Page 493: ...ET TYPE RESET VALUE DESCRIPTION PIDR 0x00 RW 0x00000000 Port I Data Register PJDR 0x04 RW 0x00000000 Port J Data Register PIDDR 0x08 RW 0x00000000 Port I Data Direction Register 0x0C Reserved Reserved PGDR 0x00 RW 0x00000000 Port G Data Register PHDR 0x04 RW 0x00000000 Port H Data Register PGDDR 0x08 RW 0x00000000 Port G Data Direction Register PHDDR 0x0C RW 0x00000000 Port H Data Direction Regist...

Page 494: ...00 BTR1 0x1C R RW Bus Timing 1 Register 0x00 0x20 Reserved 0x24 Reserved 0x28 Reserved returns 00h when read ALC 0x02C R R Arbitration Lost Capture Register 0x00 ECC 0x30 R R Error Code Capture Register 0x00 EWLR 0x34 R RW Error Warning Limit Register 0x60 RXERR 0x38 R RW Receive Error Counter Register 0x00 TXERR 0x3C R RW Transmit Error Counter Register 0x00 Transmit Buffer 0x40 W RW Transmit Fra...

Page 495: ...ing Register PC 0x10 RW 0x0000 Power Configuration Register GC 0x14 RW 0x0000 General Configuration Register GS 0x18 R 0x0210 General Status Register IS 0x1C R 0x0010 Interrupt Status Register FS 0x20 R 0x0004 FIFO Status Register HWCB0 HWCB15 0x24 0x60 RW 0x0000 High Word Control Bank Registers LWCB0 LWCB15 0x64 0xA0 RW 0x0000 Low Word Control Bank Registers IHWCTRL 0xA4 RW 0x0000 Idle High Word ...

Page 496: ...erts data into a suitable format for the slave devices on the APB It is a slave on the AHB and the only bus master on the APB ARM7TDMI S Core Synthesizeable version of the ARM7TDMI Central Processing Unit belonging to the ARM7 family of processors For more information see the ARM Ltd website www arm com Big endian The most significant byte or half word of the data is stored at the lowest storage a...

Page 497: ...ype of color Liquid Crystal Display that uses transmitted light to form a display Embedded SRAM Static Random Access Memory that is present in the processor for application use The LH75400 01 10 11 has 32KB of embedded SRAM eSRAM Endianness Describes the bit byte or word sequence of data communication or storage associating the most significant or least significant end of a data sequence with the ...

Page 498: ...l Synchronization Pulse Width The HSW is the width of the pixel clock when in passive mode or the width of the horizontal synchronization pulse in active mode The required width may vary from one LCD panel to another and the required HSW width should be determined from the particular LCD data sheet IrDA Infrared Data Association More commonly IrDA refers to the specification defined and maintained...

Page 499: ...ocontroller or SoC Mask Bit pattern or by itself to disable A Masking register enables or disables something MB Megabyte 1 024K MSb Most significant bit of a byte half word or word MSB Most significant byte of a half word or word MSW Most significant word of an ordered sequence Non Volatile Memory A memory technology that retains its contents when power is removed Examples are ROM and Flash Also s...

Page 500: ...ed light to form a display SWI Software Interrupt An SWI causes an interrupt to be asserted due to a decision within the software rather than in response to a hardware stimulus SWIs can be assigned priority within the VIC just as hardware interrupts TCM Tightly Coupled Memory Memory that is directly connected to CPU core bypassing the AHB Allows the CPU core to access this memory without AHB acces...

Page 501: ...tion signal indexes Volatile Memory A general term for any memory technology that loses its contents when power is removed Examples are RAM SRAM and SDRAM See Non Volatile Memory VSW Vertical Synchronization Pulse Width The quantity of vertical synchronization lines fed to an LCD panel W In register tables Write Only Write Only fields should not be read as the data is invalid WDT Watchdog Timer Th...

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