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LH75400/01/10/11 (Preliminary) User’s Guide
Liquid Crystal Display Controller
6/17/03
14-7
14.3 LCDC Programmer’s Model
The base address for the LCDC is:
LDC Base Address: 0xFFFF4000
The following locations are reserved and must not be used during normal operation:
• Locations at offsets 0x030 through 0x1FC
• Locations at offsets 0x400 through 0x7FF.
14.3.1 LCDC Register Summary
Table 14-6. LCDC Register Summary
NAME
ADDRESS
OFFSET
TYPE
RESET
VALUE
DESCRIPTION
Timing0
0x000
RW
0x00000000 Horizontal Timing Panel Control Register
Timing1
0x004
RW
0x00000000 Vertical Timing Panel Control Register
Timing2
0x008
RW
0x0000000 Clock and Signal Polarity Control Register
///
0x00C
RW
Reserved
UPBASE
0x010
RW
0x0000000 Upper Panel Frame Buffer Base Address Register
LPBASE
0x014
RW
0x00000000 Lower Panel Frame Buffer Base Address Register
INTRENABLE
0x018
RW
0x00000000 Interrupt Enable Register
CTRL
0x01C
RW
0x0000
LCD Panel Parameters, LCD Panel Power, and
LCDC Control Register
Status
0x020
RW
0x00000000 Raw Interrupt Status Register
Interrupt
0x024
R
0x00000000 Final Masked Interrupts Register
UPCURR
0x028
R
0x00000000 Upper Panel Frame Buffer Current Address Register
LPCURR
0x02C
R
0x00000000 Lower Panel Frame Buffer Current Address Register
///
0x030 - 0x1FC
0x00000
Reserved
Palette
0x200 - 0x3FC
RW
LCD Palette Register. Palette is addressed at 32 bits
///
0x400 - 0x7FF
Reserved