Rohde & Schwarz NRPM OTA Power Measurement Solution, Manual

Page: 100 / 229

Network and remote operation
R&S
®
NRPM
100 Mannual 1425.8663.02 ─ 08
Bit No. Meaning
2 Error queue not empty
The bit is set if the error queue has an entry. If this bit is enabled by the SRE,
each entry of the error queue generates a service request. An error can thus be
recognized and specified in detail by querying the error queue. The query yields a
conclusive error message. This procedure is recommended since it considerably
reduces the problems of IEC/IEEE-bus control.
3 Questionable status register summary bit
This bit is set if an
EVENt
bit is set in the
QUEStionable
status register and the
associated
ENABLe
bit is set to 1. A set bit denotes a questionable device status
which can be specified in greater detail by querying the QUEStionable Status
Register.
See
Chapter 9.2.6, "Questionable status register" , on page 102.
4 MAV bit (Message available)
This bit is set if a readable message is in the output queue. This bit may be used
to automate reading of data from the sensor module into the controller.
5 ESB: Standard event status register summary bit
This bit is set if one of the bits in the standard event status register is set and
enabled in the event status enable register. Setting this bit denotes a serious error
which can be specified in greater detail by querying the standard event status
register.
See
Chapter 9.2.7, "Standard event status and enable register (ESR, ESE)" ,
on page 104.
6 MSS: Master status summary bit
This bit is set if the sensor module triggers a service request. This is the case if
one of the other bits of this register is set together with its enable bit in the service
request enable register (SRE).
7 Operation status register summary bit
This bit is set if an
EVENt
bit is set in the operation status register and the associ-
ated
ENABLe
bit is set to 1. A set bit denotes that an action is being performed by
the sensor module. Information on the type of action can be obtained by querying
the operation status register.
See
Chapter 9.2.8, "Operation status register" , on page 105.
9.2.4 IST flag and parallel poll enable register (PPE)
Similar to the SRQ, the IST flag combines the complete status information in a
single bit. It can be queried by a parallel poll or by the
*IST?
command.
The Parallel Poll Enable Register (PPE) determines which bits of the STB affect
the IST flag. The bits of the STB are ANDed with the corresponding bits of the
Status reporting system