Rev. 3.00 Mar. 14, 2006 Page 800 of 804
REJ09B0104-0300
Exception handling by illegal
instruction................................................. 84
Exception handling vector table ............... 74
Exception-handling state .......................... 64
Extended repeat area............................... 156
Extended repeat area function ................ 170
External bus clock (B
φ
) .................. 128, 661
External clock......................................... 666
External interrupts .................................. 103
External trigger input.............................. 560
F
Flash erase block select parameter ......... 597
Flash memory ......................................... 569
Flash multipurpose address area
parameter ................................................ 595
Flash multipurpose data destination
parameter ................................................ 596
Flash pass and fail parameter.................. 589
Flash program/erase frequency
parameter ................................................ 594
Free-running count operation ................. 300
Frequency divider........................... 661, 666
Full-scale error........................................ 561
G
General illegal instruction ........................ 84
General registers....................................... 29
H
Hardware protection ............................... 623
HCAN halt mode.................................... 500
HCAN sleep mode.................................. 498
HCAN transmission setting .................... 507
I
I/O ports .................................................. 205
ID code.................................................... 416
Illegal instruction ...................................... 83
Input buffer control register .................... 213
Input capture function............................. 303
Internal bus ............................................. 129
Internal interrupts.................................... 104
Internal peripheral bus ............................ 127
Internal system bus 1 .............................. 127
Interrupt .................................................... 81
Interrupt control mode 0 ......................... 112
Interrupt control mode 2 ......................... 114
Interrupt controller.................................... 87
Interrupt exception handling ..................... 82
Interrupt exception handling sequence ... 116
Interrupt exception handling
vector table.............................................. 105
Interrupt response times.......................... 117
Interrupt sources ..................................... 103
Interrupt sources and vector address
offsets...................................................... 105
Interval timer mode................................. 373
Inverse convention.................................. 431
IRQn interrupts ....................................... 103
M
Mailbox................................................... 478
Mark state ....................................... 405, 442
MCU operating modes.............................. 67
Memory MAT configuration .................. 573
Message control ...................................... 478
Message data........................................... 481
Message transmission cancellation ......... 492
Message transmission method ................ 489
Mode 1 ...................................................... 71
Mode 2 ...................................................... 71
Mode 3 ...................................................... 71
Mode pin................................................... 67
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