Section 13 Controller Area Network (HCAN)
Rev. 3.00 Mar. 14, 2006 Page 459 of 804
REJ09B0104-0300
13.3.5
Transmit Wait Register (TXPR)
TXPR makes transmit messages stored in mailboxes enter the transmit wait state (CAN bus
arbitration wait).
15
TXPR7
0
R/W
14
TXPR6
0
R/W
13
TXPR5
0
R/W
12
TXPR4
0
R/W
11
TXPR3
0
R/W
8
—
1
R
10
TXPR2
0
R/W
9
TXPR1
0
R/W
Bit
Bit Name
Initial Value
R/W
7
TXPR15
0
R/W
6
TXPR14
0
R/W
5
TXPR13
0
R/W
4
TXPR12
0
R/W
3
TXPR11
0
R/W
0
TXPR8
0
R/W
2
TXPR10
0
R/W
1
TXPR9
0
R/W
Bit
Bit Name
Initial Value
R/W
Bit Bit
Name
Initial
Value R/W
Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXPR7
TXPR6
TXPR5
TXPR4
TXPR3
TXPR2
TXPR1
TXPR15
TXPR14
TXPR13
TXPR12
TXPR11
TXPR10
TXPR9
TXPR8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
These bits set a transmit wait (CAN bus arbitration
wait) for the corresponding mailboxes 1 to 15.
When TXPRn (n = 1 to 15) is set to 1, the
message in mailbox n becomes the transmit wait
state.
[Clearing conditions]
Completion of message transmission
Completion of transmission cancellation
Bit 8 is reserved. This is a read-only bit and cannot
be modified.
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