Renesas H8SX series, Hardware Manual

Page: 377 / 846

Section 9 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Mar. 14, 2006 Page 339 of 804
REJ09B0104-0300
9.9.5 Conflict between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented. Figure 9.48 shows the timing in this case.
P
φ
TCNT input
clock
TCNT N
Address
Write
T1 T2
TCNT write cycle
M
TCNT write data
TCNT
address
Figure 9.48 Conflict between TCNT Write and Increment Operations
9.9.6 Conflict between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is disabled. A compare match also does not occur when the same
value as before is written.
Figure 9.49shows the timing in this case.
TGR
Compare match
signal
P
φ
TCNT N
+
1 N
Address
Write
T1 T2
M
TGR
address
TGR write cycle
N
Disabled
TGR write data
Figure 9.49 Conflict between TGR Write and Compare Match
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