Renesas H8SX series Page 233 Hardware Manual Download | Manualshive

Page: 233 / 846

background image

Section 7 DMA Controller (DMAC)

Rev. 3.00 Mar. 14, 2006 Page 195 of 804

REJ09B0104-0300

(5)

Activation Timing by

DREQ

Low Level with NRD = 1

When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is
delayed for one cycle.

Figure 7.37 shows an example of single address mode activated by the

DREQ

signal low level

with NRD = 1.

The

DREQ

signal is sampled every cycle from the next rising edge of the B

φ

signal immediately

after the DTE bit write cycle.

When a low level of the

DREQ

signal is detected while a transfer request by the

DREQ

signal is

enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after one cycle of the transfer
request duration inserted by NRD = 1 on completion of the single cycle and then a low level of the

DREQ

signal is detected. This operation is repeated until the transfer is completed.

Min. of 3 cycles

Min. of 3 cycles

DMA single

cycle

DMA single

cycle

B

φ

DREQ

Address bus

Channel

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[1]

After DMA transfer request is enabled, a low level of the

DREQ

signal is detected at the rising edge of the B

φ

signal and a transfer

request is held.

[2][5]  The DMAC is activated and the transfer request is cleared.
[3][6]  A DMA cycle is started.
[4][7]  Transfer request enable is resumed one cycle after completion of the single cycle.

(A low level of the

DREQ

signal is detected at the rising edge of the B

φ

signal and a transfer request is held. This is the same as [1].)

Transfer source/

Transfer destination

Bus

released

Bus

released

Transfer request

enable resumed

Transfer request

enable resumed

Transfer source/

Transfer destination

Request

Request

Duration of transfer

request disabled

Duration of transfer

request disabled

Duration of transfer request

disabled which is extended

by NRD

Duration of transfer request

disabled which is extended

by NRD

Bus

released

Figure 7.37 Example of Transfer in Single Address Mode Activated

by

DREQ

Low Level with NRD = 1

Downloaded from

electronic components distributor

«
...
231
232
233
234
235
...
»

Summary of Contents for H8SX series

Page 1: ...6 32 H8SX 1520Group Hardware Manual Renesas 32 Bit CISC Microcomputer H8SX Family H8SX 1500 Series H8SX 1527 R5F61527 H8SX 1525 R5F61525 Rev 3 00 REJ09B0104 0300 Downloaded from Elcodis com electronic...

Page 2: ...Rev 3 00 Mar 14 2006 Page ii of xxxviii Downloaded from Elcodis com electronic components distributor...

Page 3: ...a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting from the information contained...

Page 4: ...first supplied the product s state is undefined The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin During the peri...

Page 5: ...put Pin iii Register Description iv Operation v Usage Note When designing an application system that includes this LSI take notes into account Each section includes notes in relation to the descriptio...

Page 6: ...s on the CPU system control functions and peripheral functions In order to understand the details of the CPU s functions Read the H8SX Family Software Manual In order to understand the details of a re...

Page 7: ...6 Page vii of xxxviii H8SX 1520 Group manuals Document Title Document No H8SX 1520 Group Hardware Manual This manual H8 SX Family Software Manual REJ09B0102 Downloaded from Elcodis com electronic comp...

Page 8: ...Rev 3 00 Mar 14 2006 Page viii of xxxviii Downloaded from Elcodis com electronic components distributor...

Page 9: ...m Counter PC 30 2 5 3 Condition Code Register CCR 30 2 5 4 Extended Control Register EXR 32 2 5 5 Vector Base Register VBR 32 2 5 6 Short Address Base Register SBR 32 2 5 7 Multiply Accumulate Registe...

Page 10: ...fective Address Calculation 61 2 8 13 MOVA Instruction 63 2 9 Processing States 64 Section 3 MCU Operating Modes 67 3 1 Operating Mode Selection 67 3 2 Register Descriptions 68 3 2 1 Mode Control Regi...

Page 11: ...er ISR 101 5 3 7 Software Standby Release IRQ Enable Register SSIER 102 5 4 Interrupt Sources 103 5 4 1 External Interrupts 103 5 4 2 Internal Interrupts 104 5 5 Interrupt Exception Handling Vector Ta...

Page 12: ...36 7 2 1 DMA Source Address Register DSAR 137 7 2 2 DMA Destination Address Register DDAR 138 7 2 3 DMA Offset Register DOFR 139 7 2 4 DMA Transfer Count Register DTCR 140 7 2 5 DMA Block Size Registe...

Page 13: ...er PnPCR n D H J and K 214 8 1 6 Open Drain Control Register PnODR n 2 215 8 1 7 Port H Realtime Input Data Register PHRTIDR 215 8 2 Output Buffer Control 216 8 2 1 Port 1 216 8 2 2 Port 2 219 8 2 3 P...

Page 14: ...sage Notes 337 9 9 1 Module Stop Mode Setting 337 9 9 2 Input Clock Restrictions 337 9 9 3 Caution on Cycle Setting 338 9 9 4 Conflict between TCNT Write and Clear Operations 338 9 9 5 Conflict betwee...

Page 15: ...4 8 Pulse Output Triggered by Input Capture 365 10 5 Usage Notes 365 10 5 1 Module Stop Mode Setting 365 10 5 2 Operation of Pulse Output Pins 365 Section 11 Watchdog Timer WDT 367 11 1 Features 367...

Page 16: ...al Data Transmission 418 12 5 2 Multiprocessor Serial Data Reception 419 12 6 Operation in Clocked Synchronous Mode 422 12 6 1 Clock 422 12 6 2 SCI Initialization Clocked Synchronous Mode 423 12 6 3 S...

Page 17: ...t Register TXPR 459 13 3 6 Transmit Wait Cancel Register TXCR 460 13 3 7 Transmit Acknowledge Register TXACK 461 13 3 8 Abort Acknowledge Register ABACK 462 13 3 9 Receive Complete Register RXPR 463 1...

Page 18: ...2 Input Output Pins 511 14 3 Register Descriptions 512 14 3 1 SS Control Register H SSCRH 514 14 3 2 SS Control Register L SSCRL 516 14 3 3 SS Mode Register SSMR 517 14 3 4 SS Enable Register SSER 518...

Page 19: ...ge Notes 563 15 7 1 Module Stop Mode Setting 563 15 7 2 Permissible Signal Source Impedance 563 15 7 3 Influences on Absolute Accuracy 564 15 7 4 Setting Range of Analog Power Supply and Other Pins 56...

Page 20: ...on 662 18 1 1 System Clock Control Register SCKCR 662 18 2 Oscillator 665 18 2 1 Connecting Crystal Resonator 665 18 2 2 External Clock Input 666 18 3 PLL Circuit 666 18 4 Frequency Divider 666 18 5 U...

Page 21: ...le Interrupts 686 19 9 5 Writing to MSTPCRA MSTPCRB and MSTPCRC 686 Section 20 List of Registers 687 20 1 Register Addresses Address Order 688 20 2 Register Bits 711 20 3 Register States in Each Opera...

Page 22: ...Rev 3 00 Mar 14 2006 Page xxii of xxxviii Downloaded from Elcodis com electronic components distributor...

Page 23: ...y Data Formats 35 Figure 2 14 Instruction Formats 53 Figure 2 15 Branch Address Specification in Memory Indirect Mode 60 Figure 2 16 State Transitions 65 Section 3 MCU Operating Modes Figure 3 1 Addre...

Page 24: ...ded Repeat Area Operation 171 Figure 7 16 Example of Extended Repeat Area Function in Block Transfer Mode 171 Figure 7 17 Address Update Method 172 Figure 7 18 Operation of Offset Addition 173 Figure...

Page 25: ...Running Counter Operation 300 Figure 9 5 Periodic Counter Operation 301 Figure 9 6 Example of Setting Procedure for Waveform Output by Compare Match 301 Figure 9 7 Example of 0 Output 1 Output Operati...

Page 26: ...and Pulse Width in Phase Counting Mode 337 Figure 9 47 Conflict between TCNT Write and Clear Operations 338 Figure 9 48 Conflict between TCNT Write and Increment Operations 339 Figure 9 49 Conflict b...

Page 27: ...r Format Transmission of Data H AA to Receiving Station A 417 Figure 12 11 Sample Multiprocessor Serial Transmission Flowchart 418 Figure 12 12 Example of SCI Operation for Reception Example with 8 Bi...

Page 28: ...re 13 7 Software Reset Flowchart 486 Figure 13 8 Detailed Description of One Bit 487 Figure 13 9 Transmission Flowchart 490 Figure 13 10 Transmit Message Cancellation Flowchart 493 Figure 13 11 Recept...

Page 29: ...nitions 562 Figure 15 8 A D Conversion Accuracy Definitions 562 Figure 15 9 Example of Analog Input Circuit 563 Figure 15 10 Example of Analog Input Protection Circuit 565 Figure 15 11 Analog Input Pi...

Page 30: ...ion 19 Power Down Modes Figure 19 1 Mode Transitions 672 Figure 19 2 Software Standby Mode Application Example 684 Section 21 Electrical Characteristics Figure 21 1 Output Load Circuit 764 Figure 21 2...

Page 31: ...Rev 3 00 Mar 14 2006 Page xxxi of xxxviii Figure 21 20 SSU Timing Slave CPHS 0 775 Appendix Figure C 1 Package Dimensions PRQP0100KB A 781 Downloaded from Elcodis com electronic components distributor...

Page 32: ...Rev 3 00 Mar 14 2006 Page xxxii of xxxviii Downloaded from Elcodis com electronic components distributor...

Page 33: ...s Ranges 58 Table 2 14 Effective Address Calculation for Transfer and Operation Instructions 62 Table 2 15 Effective Address Calculation for Branch Instructions 63 Section 3 MCU Operating Modes Table...

Page 34: ...56 Table 7 3 Transfer Modes 157 Table 7 4 List of On chip module interrupts to DMAC 167 Table 7 5 Priority among DMAC Channels 181 Table 7 6 Interrupt Sources and Priority 200 Section 8 I O Ports Tabl...

Page 35: ...ditions in Phase Counting Mode 3 322 Table 9 38 Up Down Count Conditions in Phase Counting Mode 4 323 Table 9 39 TPU Interrupts 326 Section 10 Programmable Pulse Generator PPG Table 10 1 Pin Configura...

Page 36: ...t Setting and SSRDR 525 Table 14 4 Communication Modes and Pin States of SSI and SSO Pins 528 Table 14 5 Communication Modes and Pin States of SSCK Pin 529 Table 14 6 Communication Modes and Pin State...

Page 37: ...ping Resistance Value 665 Table 18 2 Crystal Resonator Characteristics 666 Section 19 Power Down Modes Table 19 1 Operating States 671 Table 19 2 Oscillation Settling Time Settings 682 Table 19 3 B Pi...

Page 38: ...Rev 3 00 Mar 14 2006 Page xxxviii of xxxviii Downloaded from Elcodis com electronic components distributor...

Page 39: ...CI can be used in asynchronous and clocked synchronous mode Controller area network HCAN Synchronous serial communication unit SSU 10 bit A D converter Clock pulse generator Note Supported only by the...

Page 40: ...tral processing unit DMAC DMA controller BSC Bus controller WDT Watchdog timer TPU 16 bit timer pulse unit PPG Programmable pulse generator SCI Serial communication interface HCAN Controller area netw...

Page 41: ...ing unit DMAC DMA controller BSC Bus controller WDT Watchdog timer TPU 16 bit timer pulse unit SCI Serial communication interface HCAN Controller area network SSU Synchronous communication unit TPU un...

Page 42: ...OCC3 IRQ10 A P21 TIOCA3 IRQ9 A SCS2 P20 TIOCA3 TIOCB3 IRQ8 A P17 ADTRG1 IRQ7 P16 SCK3 IRQ6 P15 RxD3 IRQ5 P14 TxD3 IRQ4 P13 ADTRG0 IRQ3 P12 IRQ2 VCL P11 IRQ1 Vss P10 IRQ0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH...

Page 43: ...RQ4 P13 ADTRG0 IRQ3 P12 IRQ2 VCL P11 IRQ1 Vss P10 IRQ0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PK7 TIOCA11 TIOCB11 PK6 TIOCA11 PK5 TIOCA10 TIOCB10 PK4 TIOCA10 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242...

Page 44: ...4 IRQ9 B 7 P62 SCK4 IRQ10 B 8 P63 IRQ11 B TDO 2 9 P64 IRQ12 HTxD 10 P65 IRQ13 HRxD 11 P66 IRQ14 12 PJ0 TIOCA6 13 PJ1 TIOCA6 TIOCB6 14 PJ2 TIOCC6 TCLKE 15 PJ3 TIOCC6 TIOCD6 TCLKF 16 PJ4 TIOCA7 17 PJ5 T...

Page 45: ...1 VCL 42 P12 IRQ2 43 P13 ADTRG0 IRQ3 44 P14 TxD3 IRQ4 45 P15 RxD3 IRQ5 46 P16 SCK3 IRQ6 47 P17 ADTRG1 IRQ7 48 P20 TIOCA3 TIOCB3 1 IRQ8 A 49 P21 TIOCA3 1 IRQ9 A SCS2 50 P22 TIOCC3 1 IRQ10 A 51 P23 TIOC...

Page 46: ...IOCB1 TCLKC 1 TMS 2 64 P36 PO14 TIOCA2 1 TDI 2 65 P37 PO15 TIOCA2 TIOCB2 TCLKD 1 TCK 2 66 RES 67 NMI 68 Vcc 69 XTAL 70 EXTAL 71 Vss 72 EMLE 2 73 PA3 SSO2 74 PA2 SSI2 75 PA1 SSCK2 76 MD1 77 P40 AN12 78...

Page 47: ...D0 97 PD0 SSO0 98 PD1 SSI0 99 PD2 SSCK0 100 PD3 SCS0 Notes 1 Not supported by the H8SX 1525 2 The EMLE emulator enable pin enables disables the on chip debugging functions When the EMLE pin is driven...

Page 48: ...69 69 Input EXTAL 70 70 Input Pins for a crystal resonator External clock can be input to the EXTAL pin For a connection example see section 18 Clock Pulse Generator B 53 53 Output Supplies the system...

Page 49: ...44 43 42 40 38 Input Maskable interrupt request signal TRST 62 62 Input Debugging interface TMS 63 63 Input Interface pins for debugging by the on chip emulator TDO 8 8 Output TDI 64 64 Input TCK 65...

Page 50: ...These are used for the input capture inputs output compare outputs PWM outputs TIOCA7 TIOCB7 16 17 17 16 17 17 I O Signals for TGRA_7 toTGRB_7 These are used for the input capture inputs output compar...

Page 51: ...Serial communi cation interface SCI SCK3 SCK4 46 7 46 7 I O Input output pins for clock signals HTxD 9 9 Output Output pin for CAN bus transmission Controller area network HCAN HRxD 10 10 Input Input...

Page 52: ...92 91 90 89 87 Input Input pins for the analog signals for the A D converter ADTRG0 ADTRG1 43 47 43 47 Input Input pins for the external trigger signal to start A D conversion AVCC0 AVCC1 88 84 88 84...

Page 53: ...42 40 38 47 46 45 44 43 42 40 38 I O 8 bit input output pins P23 P22 P21 P20 51 50 49 48 51 50 49 48 I O 4 bit input output pins P37 P36 P35 P34 P33 P32 P31 P30 65 64 63 62 61 60 59 58 65 64 63 62 61...

Page 54: ...94 93 92 91 90 89 87 Input 8 bit input pins P66 P65 P64 P63 P62 P61 P60 11 10 9 8 7 6 5 11 10 9 8 7 6 5 I O 7 bit input output pins PA7 53 53 Input 1 bit input pin PA6 PA5 PA4 PA3 PA2 PA1 55 56 57 73...

Page 55: ...7 36 35 34 33 32 31 30 37 36 35 34 33 32 31 30 I O 8 bit input output pins PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 19 18 17 16 15 14 13 12 19 18 17 16 15 14 13 12 I O 8 bit input output pins PK7 PK6 PK5 PK4 P...

Page 56: ...Section 1 Overview Rev 3 00 Mar 14 2006 Page 18 of 804 REJ09B0104 0300 Downloaded from Elcodis com electronic components distributor...

Page 57: ...nstructions Multiply and divide instructions Bit field transfer instructions Powerful bit manipulation instructions Bit condition branch instructions Multiply and accumulate instruction Eleven address...

Page 58: ...ate 32 16 bit register register divide 18 states 32 32 bit register register multiply 5 states 32 32 bit register register divide 18 states Four CPU operating modes Normal mode Middle mode Advanced mo...

Page 59: ...table and stack have the same structure as in the H8 300 CPU Note Normal mode is not supported in this LSI Address Space The maximum address space of 64 kbytes can be accessed Extended Registers En T...

Page 60: ...irect vec 7 addressing modes are used in the JMP and JSR instructions An 8 bit absolute address included in the instruction code specifies a memory location Execution branches to the contents of the m...

Page 61: ...affected Instruction Set All instructions and addressing modes can be used Only the lower 16 bits of effective addresses EA are valid and the upper eight bits are sign extended Exception Vector Table...

Page 62: ...ated to the exception vector table One branch address is stored per 32 bits The upper eight bits are ignored and the lower 24 bits are stored The structure of the exception vector table is shown in fi...

Page 63: ...2 4 Maximum Mode The program area is extended to 4 Gbytes as compared with that in advanced mode Address Space The maximum address space of 4 Gbytes can be linearly accessed Extended Registers En The...

Page 64: ...pecifies a memory location Execution branches to the contents of the memory location In maximum mode an operand is a 32 bit longword operand providing a 32 bit branch address Stack Structure The stack...

Page 65: ...ote In the H8SX 1520 Group an instruction is fetched in 32 bit mode 2 4 Address Space Figure 2 8 shows a memory map of the H8SX CPU The address space differs depending on the CPU operating mode H 0000...

Page 66: ...R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L General Registers and Extended Registers Control Registers Legend Stack pointer Program counter Condition code register Interrupt mask bit User...

Page 67: ...gisters are used as 8 bit registers the R registers are divided into 8 bit general registers designated by the letters RH R0H to R7H and RL R0L to R7L These registers are functionally equivalent provi...

Page 68: ...information including an interrupt mask I and user UI U bits and half carry H negative N zero Z overflow V and carry C flags Operations can be performed on the CCR bits by the LDC STC ANDC ORC and XOR...

Page 69: ...U Undefined R W User Bit Can be written to and read from by software using the LDC STC ANDC ORC and XORC instructions 3 N Undefined R W Negative Flag Stores the value of the most significant bit regar...

Page 70: ...W Interrupt Mask Bits These bits designate the interrupt mask level 0 to 7 2 5 5 Vector Base Register VBR VBR is a 32 bit register in which the upper 20 bits are valid The lower 12 bits of this regis...

Page 71: ...to 0 and sets the I bits in CCR and EXR to 1 The general registers MAC and the other bits in CCR are not initialized In particular the initial value of the stack pointer ER7 is undefined The SP should...

Page 72: ...Word data Longword data RnH RnL RnH RnL RnH RnL Rn En ERn MSB Don t care Upper Lower 4 3 7 0 Don t care 7 0 Don t care 7 0 General register ER General register E General register R General register R...

Page 73: ...case these accesses are assumed to be individual bus cycles However instructions to be fetched word and longword data to be accessed during execution of the stack manipulation branch table manipulatio...

Page 74: ...W L 6 MOVFPE 6 MOVTPE 6 B POP PUSH 1 W L LDM STM L MOVA B W 2 Block transfer EEPMOV B 3 MOVMD B W L MOVSD B Arithmetic operations ADD ADDX SUB SUBX CMP NEG INC DEC B W L 27 DAA DAS B ADDS SUBS L MULX...

Page 75: ...e size W Word size L Longword size Notes 1 POP W Rn and PUSH W Rn are identical to MOV W SP Rn and MOV W Rn SP POP L ERn and PUSH L ERn are identical to MOV L SP ERn and MOV L ERn SP 2 Size of data to...

Page 76: ...aa 32 MOV B W L S SD SD SD SD SD SD B S D S D MOVFPE MOVTPE 12 B S D S D 1 POP PUSH W L S D S D 2 LDM STM L S D S D 2 Data transfer MOVA 4 B W S S S S S S EEPMOV B SD 3 MOVMD B W L SD 3 Block transfe...

Page 77: ...D D EXTU EXTS W L D D D D D D TAS B D MAC CLRMAC O LDMAC S STMAC D B S D D D D D D B D S S S S S S B SD SD SD SD SD AND OR XOR W L S SD SD SD SD SD SD NOT B D D D D D D D Logic operations W L D D D D...

Page 78: ...perand or both S D Can be specified as either a source or destination operand S 4 4 bit immediate data can be specified as a source operand Notes 1 Only aa 16 is available 2 ERn as a source operand an...

Page 79: ...e Classifi cation Instruction Size ERn d PC RnL B Rn W ERn L PC aa 24 aa 32 aa 8 vec 7 Branch BRA BS BRA BC O BSR BS BSR BC O Bcc O BRA O O BRA S O JMP O O O O O BSR O JSR O O O O O RTS RTS L O TRAPA...

Page 80: ...ource operand EXR Extended control register CCR Condition code register VBR Vector base register SBR Short address base register N N negative flag in CCR Z Z zero flag in CCR V V overflow flag in CCR...

Page 81: ...r list Restores the data from the stack to multiple general registers Two three or four general registers which have serial register numbers can be specified STM L Rn register list SP Saves the conten...

Page 82: ...ock Transfers word data which begins at a memory location specified by ER5 to a memory location specified by ER6 The number of word data to be transferred is specified by R4 MOVMD L L Transfers a data...

Page 83: ...or from data in a general register DAA DAS B Rd decimal adjust Rd Decimal adjusts an addition or subtraction result in a general register by referring to the CCR to produce 2 digit 4 bit BCD data MULX...

Page 84: ...EAs Compares data between immediate data general registers and memory and stores the result in CCR NEG B W L 0 EAd EAd Takes the two s complement arithmetic complement of data in a general register o...

Page 85: ...a logical AND operation on data between immediate data general registers and memory OR B W L EAd IMM EAd EAd EAs EAd Performs a logical OR operation on data between immediate data general registers an...

Page 86: ...e the number of bits is specified by 5 bit immediate data or the lower 5 bits of the contents of a general register SHAL SHAR B W L EAd shift EAd Performs an arithmetic shift on the contents of a gene...

Page 87: ...of a general register The Z flag status can be specified as a condition BNOT B bit No of EAd bit No of EAd Inverts a specified bit in the contents of a general register or a memory location The bit nu...

Page 88: ...te data BLD B bit No of EAd C Transfers a specified bit in the contents of a general register or a memory location to the carry flag The bit number is specified by 3 bit immediate data BILD B bit No o...

Page 89: ...If the specified condition is satisfied execution branches to a specified address BSR BS BSR BC B Tests a specified bit in memory location contents If the specified condition is satisfied execution b...

Page 90: ...them and memory The upper 8 bits are valid LDC L Rs VBR Rs SBR Transfers the general register contents to VBR or SBR B W CCR EAd EXR EAd Transfers the contents of CCR or EXR to a general register or m...

Page 91: ...address extension and condition field op cc EA disp BRA d 16 etc Figure 2 14 Instruction Formats Operation Field Indicates the function of the instruction and specifies the addressing mode and operati...

Page 92: ...Addressing Mode Symbol 1 Register direct Rn 2 Register indirect ERn 3 Register indirect with displacement d 2 ERn d 16 ERn d 32 ERn 4 Index register indirect with displacement d 16 RnL B d 16 Rn W d...

Page 93: ...sed in a branch instruction the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 H 00 2 8 3 Register Indirect with Displacement d 2 ERn d 16 ERn or d 32 ERn The operand value is th...

Page 94: ...register ERn ERn is specified by the register field of the instruction code After the memory location is accessed 1 2 or 4 is added to the address register contents and the sum is stored in the addres...

Page 95: ...ter which is also used as an address register is written to memory using this addressing mode data to be written is the contents of the general register after calculating an effective address If the s...

Page 96: ...the entire address space To access the program area the absolute address of 24 bits aa 24 or 32 bits aa 32 is used For a 24 bit absolute address the upper 8 bits are all assumed to be 0 H 00 Table 2 1...

Page 97: ...he 32 bit address of the PC contents The 8 bit or 16 bit displacement is sign extended to 32 bits when added to the PC contents The PC contents to which the displacement is added is the address of the...

Page 98: ...nd the branch address is 16 bits long In other modes the memory location is pointed to by longword size data In middle or advanced mode the first byte of the longword size data is assumed to be all 0...

Page 99: ...branch address is 16 bits long In other modes the memory location is pointed to by longword size data In middle or advanced mode the first byte of the longword size data is assumed to be all 0 H 00 2...

Page 100: ...ister direct Register indirect Register indirect with 16 bit displacement Register indirect with 32 bit displacement Index register indirect with 16 bit displacement Index register indirect with 32 bi...

Page 101: ...ress Calculation Effective Address EA PC contents Sign extension PC contents Zero extension Zero extension Memory contents Memory contents Zero extension PC contents Program counter relative with 16 b...

Page 102: ...state The exception handling state is a transient state that occurs when the CPU alters the normal processing flow due to activation of an exception source such as a reset trace interrupt or trap ins...

Page 103: ...e watchdog timer overflows Note Reset state Exception handling state Request for exception handling End of exception handling Program execution state Bus released state Bus request End of bus request...

Page 104: ...Section 2 CPU Rev 3 00 Mar 14 2006 Page 66 of 804 REJ09B0104 0300 Downloaded from Elcodis com electronic components distributor...

Page 105: ...mode and user boot mode for programming erasing the flash memory and single chip initiation mode Table 3 1 MCU Operating Mode Settings MCU Operating Mode MD1 MD0 CPU Operating Mode Address Space Desc...

Page 106: ...lue R W Note Determined by pins MD1 and MD0 15 0 R 14 1 R 13 0 R 12 1 R 11 MDS3 Undefined R 10 MDS2 Undefined R 9 MDS1 Undefined R 8 MDS0 Undefined R Bit Bit Name Initial Value R W 7 0 R 6 1 R 5 0 R 4...

Page 107: ...MSD3 to MSD0 MDCR MCU Operating Mode MD1 MD0 MDS3 MDS2 MDS1 MDS0 1 0 1 1 1 0 1 2 1 0 1 1 0 0 3 1 1 0 1 0 0 3 2 2 System Control Register SYSCR SYSCR controls MAC saturation operation and enables disab...

Page 108: ...M Enable Enables or disables the on chip RAM This bit is initialized when the reset state is released Do not write 0 during access to the on chip RAM 0 On chip RAM disabled 1 On chip RAM enabled 7 FLS...

Page 109: ...s that in mode 3 other than programming erasing the flash memory 3 3 2 Mode 2 Mode 2 is the boot mode for the flash memory The operations are the same as that in mode 3 other than programming erasing...

Page 110: ...dress map Mode 1 to mode 3 Single chip initiation mode advanced mode On chip RAM 12 kbytes On chip ROM 256 kbytes Reserved Reserved Reserved On chip I O register On chip I O register H 000000 H 040000...

Page 111: ...watchdog timer overflows The CPU enters the reset state when the RES pin is low Illegal instruction Exception handling starts when an undefined code is executed Trace 1 Exception handling starts after...

Page 112: ...3 MCU Operating Modes Table 4 2 Exception Handling Vector Table Vector Table Address Offset 1 Exception Source Vector Number Normal Mode 2 Advanced Middle Maximum Modes Reset 0 H 0000 to H 0001 H 0000...

Page 113: ...o H 0091 H 0120 to H 0123 IRQ9 73 H 0092 to H 0093 H 0124 to H 0127 IRQ10 74 H 0094 to H 0095 H 0128 to H 012B IRQ11 75 H 0096 to H 0097 H 012C to H 012F IRQ12 76 H 0098 to H 0099 H 0130 to H 0133 IRQ...

Page 114: ...in low for at least 20 cycles The chip can also be reset by overflow of the watchdog timer For details see section 11 Watchdog Timer WDT A reset initializes the internal state of the CPU and the regis...

Page 115: ...reset state is released MSTPCRA MSTPCRB and MSTPCRC are initialized to H 0FFF H FFFF and H FF00 respectively and all modules except the DMAC enter module stop mode Consequently on chip peripheral mod...

Page 116: ...ows the state of CCR and EXR after execution of trace exception handling Trace mode is canceled by clearing the T bit in EXR to 0 during the trace exception handling However the T bit saved on the sta...

Page 117: ...ral module space 1 Occurs Fetches instructions from external memory space in single chip mode Occurs Fetches instructions from access reserved area 2 Occurs Stack operation CPU Accesses stack when the...

Page 118: ...rror exception handling is as follows 1 The contents of PC CCR and EXR are saved in the stack 2 The interrupt mask bit is updated and the T bit is cleared to 0 3 An exception handling vector table add...

Page 119: ...Type Source Number of Sources NMI NMI pin external input 1 IRQ0 to IRQ14 Pins IRQ0 to IRQ11 external input 15 Watchdog timer WDT 1 A D converter 2 On chip peripheral module 16 bit timer pulse unit TPU...

Page 120: ...ndling and the vector address differ depending on the product For details refer to section 5 Interrupt Controller The interrupt exception handling is as follows 1 The contents of PC CCR and EXR are sa...

Page 121: ...nd the T bit is cleared to 0 3 An exception handling vector table address corresponding to the vector number specified in the TRAPA instruction is generated the start address of the exception service...

Page 122: ...ys executable in the program execution state The exception handling for the general illegal and a slot illegal instructions is as follows 1 The contents of PC CCR and EXR are saved in the stack 2 The...

Page 123: ...ling Figure 4 2 shows the stack after completion of exception handling CCR PC 24 bits SP EXR Reserved CCR PC 24 bits SP Advanced mode Interrupt control mode 0 Interrupt control mode 2 Note Ignored on...

Page 124: ...W Rn or MOV W SP Rn POP L ERn or MOV L SP ERn Performing stack manipulation while SP is set to an odd value leads to an address error Figure 4 3 shows an example of operation when the SP value is odd...

Page 125: ...rror Independent vector addresses All interrupt sources are assigned independent vector addresses making it unnecessary for the source to be identified in the interrupt handling routine 16 external in...

Page 126: ...rity control register IRQ sense control register IRQ enable register ISR SSIER IPR IRQ status register Software standby release IRQ enable register Interrupt priority register Legend ISCR SSIER IER DM...

Page 127: ...er INTCR INTCR selects the interrupt control mode and the detected edge for NMI Bit Bit Name Initial Value R W 7 0 R 6 0 R 5 INTM1 0 R W 4 INTM0 0 R W 3 NMIEG 0 R W 2 0 R 1 0 R 0 0 R Bit Bit Name Init...

Page 128: ...t of the DMAC transfer The priority level of the DMAC for each channel is set by the DMAC control register Note When the IPSETE bit is set to 1 the CPU priority is automatically updated so these bits...

Page 129: ...ted in bits CPUP2 to CPUP0 2 1 0 CPUP2 CPUP1 CPUP0 0 0 0 R W R W R W CPU Priority Level 2 to 0 These bits set the CPU priority level When the CPUPCE is set to 1 the CPU priority control function over...

Page 130: ...R 14 IPR14 1 R W 13 IPR13 1 R W 12 IPR12 1 R W 11 0 R 10 IPR10 1 R W 9 IPR9 1 R W 8 IPR8 1 R W Bit Bit Name Initial Value R W 7 0 R 6 IPR6 1 R W 5 IPR5 1 R W 4 IPR4 1 R W 3 0 R 2 IPR2 1 R W 1 IPR1 1...

Page 131: ...6 IPR5 IPR4 1 1 1 R W R W R W Sets the priority level of the corresponding interrupt source 000 Priority level 0 lowest 001 Priority level 1 010 Priority level 2 011 Priority level 3 100 Priority leve...

Page 132: ...alue R W Description 15 0 R W Reserved This bit is always read as 0 The write value should always be 0 14 IRQ14E 0 R W IRQ14 Enable The IRQ14 interrupt request is enabled when this bit is 1 13 IRQ13E...

Page 133: ...it is 1 5 IRQ5E 0 R W IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1 4 IRQ4E 0 R W IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1 3 IRQ3E 0 R W IRQ3 Enable...

Page 134: ...RQn interrupt is disabled and then the IRQnF in ISR should be cleared to 0 ISCRH Bit Bit Name Initial Value R W Bit Bit Name Initial Value R W 15 0 R W 14 0 R W 13 IRQ14SR 0 R W 12 IRQ14SF 0 R W 11 IR...

Page 135: ...1 Interrupt request generated at falling edge of IRQ13 10 Interrupt request generated at rising edge of IRQ13 11 Interrupt request generated at both falling and rising edges of IRQ13 9 8 IRQ12SR IRQ12...

Page 136: ...0 R W R W IRQ9 Sense Control Rise IRQ9 Sense Control Fall 00 Interrupt request generated by low level of IRQ9 01 Interrupt request generated at falling edge of IRQ9 10 Interrupt request generated at...

Page 137: ...e of IRQ6 10 Interrupt request generated at rising edge of IRQ6 11 Interrupt request generated at both falling and rising edges of IRQ6 11 10 IRQ5SR IRQ5SF 0 0 R W R W IRQ5 Sense Control Rise IRQ5 Sen...

Page 138: ...f IRQ2 10 Interrupt request generated at rising edge of IRQ2 11 Interrupt request generated at both falling and rising edges of IRQ2 3 2 IRQ1SR IRQ1SF 0 0 R W R W IRQ1 Sense Control Rise IRQ1 Sense Co...

Page 139: ...iption 15 0 R W Reserved This bit is always read as 0 The write value should always be 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F...

Page 140: ...Bit Name Initial Value R W Description 15 0 R W Reserved This bit is always read as 0 The write value should always be 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 SSI7...

Page 141: ...RQn Interrupts An IRQn interrupt is requested by a signal input on pins IRQ14 to IRQ0 IRQn n 14 to 0 have the following features Using ISCR it is possible to select whether an interrupt is generated b...

Page 142: ...xecuted when the corresponding input signal IRQn is set to high before the interrupt handling begins 5 4 2 Internal Interrupts The sources for internal interrupts from on chip peripheral modules have...

Page 143: ...Classification Interrupt Source Vector Number Vector Address Offset 1 IPR Priority DMAC Activation External pin NMI 7 H 001C High IRQ0 64 H 0100 IPRA14 to IPRA12 IRQ1 65 H 0104 IPRA10 to IPRA8 IRQ2 66...

Page 144: ...IPRF0 O TGI1B 94 H 0178 TCI1V 95 H 017C TCI1U 96 H 0180 TPU_2 2 TGI2A 97 H 0184 IPRG14 to IPRG12 O TGI2B 98 H 0188 TCI2V 99 H 018C TCI2U 100 H 0190 TPU_3 2 TGI3A 101 H 0194 IPRG10 to IPRG8 O TGI3B 10...

Page 145: ...D0 128 H 0200 IPRI14 to IPRI12 DMTEND1 129 H 0204 IPRI10 to IPRI8 DNTEND2 130 H 0208 IPRI6 to IPRI4 DMTEND3 131 H 020C IPRI2 to IPRI0 Reserved for system use 132 H 0210 133 H 0214 134 H 0218 135 H 021...

Page 146: ...RXI4 161 H 0284 O TXI4 162 H 0288 O TEI4 163 H 028C TPU_6 TGI6A 164 H 0290 IPRL2 to IPRL0 O TGI6B 165 H 0294 TGI6C 166 H 0298 TGI6D 167 H 029C TCI6V 168 H 02A0 IPRM14 to IPRM12 TPU_7 TGI7A 169 H 02A4...

Page 147: ...185 H 02E4 TCI10V 186 H 02E8 IPRO14 to IPRO12 TCI10U 187 H 02EC TPU_11 TGI11A 188 H 02F0 IPRO10 to IPRO8 O TGI11B 189 H 02F4 TCI11V 190 H 02F8 IPRO6 to IPRO4 TCI11U 191 H 02FC Reserved for system use...

Page 148: ...served for system use 224 H 0380 IPRR14 to IPRR12 225 H 0384 226 H 0388 SSERI0 227 H 038C SSRXI0 228 H 0390 IPRR10 to IPRR8 O SSTXI0 229 H 0394 O SSU_1 Reserved for system use 230 H 0398 SSERI1 231 H...

Page 149: ...ress Offset 1 IPR Priority DMAC Activation Reserved for system use 246 H 03D8 High 247 H 03DC 248 H 03E0 249 H 03E4 250 H 03E8 251 H 03EC 252 H 03F0 253 H 03F4 254 H 03F8 255 H 03FC Low Note 1 Lower 1...

Page 150: ...NMI are masked by the I bit in CCR of the CPU Figure 5 3 shows a flowchart of the interrupt acceptance operation in this case 1 If an interrupt request occurs when the corresponding interrupt enable b...

Page 151: ...ss indicated by the contents of the vector address in the vector table Program execution state Interrupt generated NMI IRQ0 IRQ1 SSTXI2 I 0 Save PC and CCR I 1 Read vector address Branch to interrupt...

Page 152: ...the selected interrupt request is compared with the interrupt mask level set in EXR When the interrupt request does not have priority over the mask level set it is held pending and only an interrupt...

Page 153: ...nterrupt Mask level 6 or below Save PC CCR and EXR Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Pending Level 1 interrupt Mask level 0 Yes Yes No Yes Yes...

Page 154: ...ling routine Internal operation Vector fetch Stack Internal operation Interrupt request signal Internal address bus Internal read signal Internal write signal Internal data bus I 1 2 4 3 5 7 Instructi...

Page 155: ...terrupt Control Mode 0 Interrupt Control Mode 2 Interrupt Control Mode 0 Interrupt Control Mode 2 Interrupt priority decision 1 3 Number of states until executing instruction ends 2 1 to 19 2 SI PC CC...

Page 156: ...he following options are available Interrupt request to the CPU Activation request to the DMAC Combination of the above For details on interrupt requests that can be used to activate the DMAC see tabl...

Page 157: ...urce must be set to lower than or equal to the DMAP settings If the CPU is given priority the DMAC may not be activated and the data transfer may be performed 2 Operation Order If the same interrupt i...

Page 158: ...ition by which the activation source is held is cancelled CPUCPCE 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DMAP2 to DMAP0 When the different priority levels of the DMAC are assi...

Page 159: ...can be assigned for each channel table 5 8 gives a single channel description Thus transfer for each channel can be performed independently by assigning the different priority levels Table 5 8 Exampl...

Page 160: ...be executed on completion of the instruction However if there is an interrupt request with priority over that interrupt interrupt exception handling will be executed for the interrupt with priority an...

Page 161: ...operation differs between the EEPMOV B and the EEPMOV W instructions With the EEPMOV B instruction an interrupt request including NMI issued during the transfer is not accepted until the transfer is c...

Page 162: ...rupt request flag of a peripheral module by the CPU the flag must be read from after being cleared within the interrupt handling routine even if the peripheral module clock is not generated by dividin...

Page 163: ...ip between the CPU and DMAC Bus mastership can be shared between the CPU and DMAC when a conflict occurs Multi clock function On chip peripheral functions can be synchronized with the on chip peripher...

Page 164: ...eserved This bit is always read as 0 The write value should always be 0 4 IBCCS 0 R W Internal Bus Cycle Control Select Selects the internal bus arbiter function 0 Releases the bus mastership accordin...

Page 165: ...M and internal peripheral bus Internal peripheral bus A bus that accesses registers in the DMAC bus controller and interrupt controller and registers of peripheral modules such as SCI and timer CPU P...

Page 166: ...6 1 Synchronization Clocks and Their Corresponding Functions Synchronization Clock Function Name I MCU operating mode Interrupt controller Bus controller CPU DMAC Internal memory Clock pulse generato...

Page 167: ...hip peripheral modules the number of access cycles differs according to the register to be accessed When the dividing ratio of the operating clock of a bus master and that of a peripheral module is 1...

Page 168: ...write data buffer function is used When this function is used if a peripheral module write continues for two cycles or longer and there is an internal access next only the peripheral module write is...

Page 169: ...n High DMAC CPU Low If the DMAC accesses continue the CPU can be given priority over the DMAC to execute the bus cycles alternatively between them by setting the IBCCS bit in BCR2 6 7 2 Bus Transfer T...

Page 170: ...r releases the bus every transfer cycle The bus cannot be transferred in the following cases Between a read cycle and the corresponding write cycle in dual address mode While the IBCCS bit in BCR2 is...

Page 171: ...source and destination are specified by addresses Single address mode Either source or destination is specified by the DREQ signal and the other is specified by address Normal repeat or block transfer...

Page 172: ...cording to its address byte or word when it is transferred Two types of interrupts can be requested to the CPU A transfer end interrupt is generated after the number of data specified by the transfer...

Page 173: ...buffer Data buffer Operation unit Operation unit Legend DSAR_n DMA source address register DREQn DMA transfer request DDAR_n DMA destination address register DACKn DMA transfer acknowledge DOFR_n DMA...

Page 174: ...MA source address register_1 DSAR_1 DMA destination address register_1 DDAR_1 DMA offset register_1 DOFR_1 DMA transfer count register_1 DTCR_1 DMA block size register_1 DBSR_1 DMA mode control regist...

Page 175: ...time data is transferred When DDAR is specified as the destination address the DIRS bit in DACR is 1 in single address mode DSAR is ignored Although DSAR can always be read from by the CPU it must be...

Page 176: ...DDAR can always be read from by the CPU it must be read from in longwords and must not be written to while data for the channel is being transferred 31 0 R W 30 0 R W 29 0 R W 28 0 R W 27 0 R W 24 0...

Page 177: ...ied for the source and destination sides of a single channel 31 0 R W 30 0 R W 29 0 R W 28 0 R W 27 0 R W 24 0 R W 26 0 R W 25 0 R W Bit Bit Name Initial Value R W 23 0 R W 22 0 R W 21 0 R W 20 0 R W...

Page 178: ...his register indicates the remaining transfer size The value corresponding to its data access size is subtracted every time data is transferred byte 1 word 2 and longword 4 Although DTCR can always be...

Page 179: ...8 BKSZ8 0 R W 10 BKSZ10 0 R W 9 BKSZ9 0 R W Bit Bit Name Initial Value R W 7 BKSZ7 0 R W 6 BKSZ6 0 R W 5 BKSZ5 0 R W 4 BKSZ4 0 R W 3 BKSZ3 0 R W 0 BKSZ0 0 R W 2 BKSZ2 0 R W 1 BKSZ1 0 R W Bit Bit Name...

Page 180: ...0 R W 29 TENDE 0 R W 28 0 R W 27 DREQS 0 R W 24 0 R 26 NRD 0 R W 25 0 R Bit Bit Name Initial Value R W 23 ACT 0 R 22 0 R 21 0 R 20 0 R 19 ERRF 0 R W 16 DTIF 0 R W 18 0 R 17 ESIF 0 R W Bit Bit Name Ini...

Page 181: ...TIF 0 R W 18 0 R 17 ESIF 0 R W Bit Bit Name Initial Value R W 15 DTSZ1 0 R W 14 DTSZ0 0 R W 13 MDS1 0 R W 12 MDS0 0 R W 11 TSEIE 0 R W 8 DTIE 0 R W 10 0 R 9 ESIE 0 R W Bit Bit Name Initial Value R W 7...

Page 182: ...nt 1 block size data transfer If an event which stops sustains a transfer occurs externally this bit is automatically cleared to 0 to stop the transfer Operating modes and transfer methods must not be...

Page 183: ...When a block transfer is performed in external request mode clear this bit to 0 to select the low level detection 0 Low level detection 1 Falling edge detection the first transfer after a transfer en...

Page 184: ...errupt has been generated However when an address error or an NMI interrupt has been generated in module stop mode this bit is not set 18 0 R Reserved This is a read only bit and cannot be modified 17...

Page 185: ...ested Clearing conditions When setting the DTE bit to 1 When clearing to 0 after reading DTIF 1 Setting condition When DTCR reaches 0 and the transfer is completed 15 14 DTSZ1 DTSZ0 0 0 R W R W Data A...

Page 186: ...sables a transfer size error interrupt request 1 Enables a transfer size error interrupt request 10 0 R Reserved This is a read only bit and cannot be modified 9 ESIE 0 R W Transfer Escape Interrupt E...

Page 187: ...t 5 DTA 0 R W Data Transfer Acknowledge This bit is valid while the DMA transfer is performed by the on chip module interrupt This bit decides whether the source flag selected by DMRSR is cleared or n...

Page 188: ...request and waits for the timing when the CPU priority becomes lower than the DMAC priority The priority levels can be set to the individual channels This bit is valid when the CPUPCE bit in CPUPCR i...

Page 189: ...alue R W 7 DARIE 0 R W 6 0 R 5 0 R 4 DARA4 0 R W 3 DARA3 0 R W 0 DARA0 0 R W 2 DARA2 0 R W 1 DARA1 0 R W Bit Bit Name Initial Value R W Bit Bit Name Initial Value R W Description 31 AMS 0 R W Address...

Page 190: ...1 to indicate that a repeat size end interrupt is requested 0 Disables a repeat size end interrupt 1 Enables a repeat size end interrupt 25 24 ARS1 ARS0 0 0 R W R W Area Select 1 and 0 Specify the bl...

Page 191: ...st for an extended area overflow on the source address When an extended repeat area overflow on the source address occurs while this bit is set to 1 the DTE bit in DMDR is cleared to 0 At this time th...

Page 192: ...estination Address Extended Repeat Area Overflow Interrupt Enable Enables disables an interrupt request for an extended area overflow on the destination address When an extended repeat area overflow o...

Page 193: ...maining upper address bits are fixed The extended repeat area size is specified from four bytes to 128 Mbytes in units of byte and a power of 2 When the lower address is overflowed from the extended r...

Page 194: ...f the address 01101 8 kbytes specified as extended repeat area by the lower 13 bits of the address 01110 16 kbytes specified as extended repeat area by the lower 14 bits of the address 01111 32 kbytes...

Page 195: ...s Mode Transfer mode Activation Source Common Function Source Destina tion Dual address Normal transfer Repeat transfer Block transfer Repeat or block size 1 to 65 536 bytes 1 to 65 536 words or 1 to...

Page 196: ...data access size or the access address is not aligned with the boundary of the data access size the number of bus cycles are needed more than two because one bus cycle is divided into multiple bus cyc...

Page 197: ...tion in dual address mode Address bus B RD WR TEND DMA read cycle DMA write cycle DSAR DDAR Figure 7 2 Example of Signal Timing in Dual Address Mode Transfer Address TA Address BA Address update setti...

Page 198: ...bus cycle The transfer direction is decided by the DIRS bit in DACR which specifies an external device with the DACK pin as the transfer source or destination When DIRS 0 data is transferred from an e...

Page 199: ...for external memory space WR signal for external memory space B Address bus Transfer from external memory to external device with DACK RD WR DACK TEND Data bus Data output by external device with DAC...

Page 200: ...fer Figure 7 7 shows an example of the signal timing in normal transfer mode and figure 7 8 shows the operation in normal transfer mode Read Write Read Write DMA transfer cycle Last DMA transfer cycle...

Page 201: ...uested to the CPU when the repeat size of transfers is completed When the next transfer is requested after completion of a 1 repeat size data transfer while the RPTIE bit is set to 1 the DTE bit in DM...

Page 202: ...the address to the transfer start address A repeat size end interrupt can be requested The TEND signal is output every time 1 block data is transferred in the last DMA transfer cycle When the externa...

Page 203: ...ddress Mode in Block Transfer Mode Block Area Specified Transfer Address TA Address BA Address TB Address BB Nth block Second block First block Nth block Second block First block BKSZH data access siz...

Page 204: ...The activation sources are specified to the individual channels Table 7 4 is a list of on chip module interrupts for the DMAC The interrupt request selected as an activation source can simultaneously...

Page 205: ...empty interrupt for SCI channel 4 SCI_4 162 TGI6A TGI6A input capture compare match TPU_6 164 TGI7A TGI7A input capture compare match TPU_7 169 TGI8A TGI8A input capture compare match TPU_8 173 TGI9A...

Page 206: ...interrupt the external request cannot be used 7 4 4 Bus Access Modes There are two types of bus access modes cycle stealing and burst When an activation source is the auto request the cycle stealing...

Page 207: ...the transfer for the channel in burst mode is completed This is similarly to operation in cycle stealing mode However setting the IBCCS bit in IBCR of the bus controller makes the DMAC release the bus...

Page 208: ...SARA0 in DACR The extended repeat area on the destination address is specified by bits DARA4 to DARA0 in DACR The extended repeat area sizes for each side can be specified independently A DMA transfer...

Page 209: ...k size boundary is aligned with the extended repeat area boundary When an overflow on the extended repeat area occurs during a transfer of one block the interrupt by the overflow is suspended and the...

Page 210: ...e not continuous a Address fixed b Increment or decrement by 1 2 or 4 c Offset addition Figure 7 17 Address Update Method In item a Address fixed the transfer source or destination address is not upda...

Page 211: ...ress B5 Address B4 4 Address A3 Address A2 Offset Address A4 Address A3 Offset Address A5 Address A4 Offset Offset Offset Offset Transfer source Offset addition Transfer destination Increment by 4 lon...

Page 212: ...e 7 19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode In figure 7 19 the source address side is specified to the repeat area by DACR and the offset addition is selected The offs...

Page 213: ...rce address Generates repeat size end interrupt request Transfer count 0 Repeat size 0 End No No Yes Yes Longword transfer Figure 7 20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer...

Page 214: ...and the address is incremented or decremented by 4 Even if the access data size of the source address is word or longword when the source address is not aligned with the word or longword boundary the...

Page 215: ...ing size is changing according to the actual data access size for example 1 or 2 for byte or word data After the one word or one longword of data is written the address when the write cycle is started...

Page 216: ...value is not changed The BKSZ bits 16 bits function as a counter for the block size and repeat size and its value is decremented every transfer by 1 When the BKSZ value is to change from 1 to 0 by a...

Page 217: ...the registers Figure 7 21 Procedure for Changing Register Setting For Channel being Transferred 6 ACT Bit in DMDR The ACT bit in DMDR indicates whether the DMAC is in the idle or active state When DTE...

Page 218: ...p a transfer after the bus cycle of the interrupt source is completed The ESIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is resumed by setting the DTE bit to...

Page 219: ...channel being transferred releases the bus At this time when a bus master other than the DMAC requests the bus the cycle for the bus master is inserted In a burst transfer or a block transfer channel...

Page 220: ...ip is passed from the DMAC to the CPU data is read from the source address and it is written to the destination address The bus is not released between the read and write cycles by other bus requests...

Page 221: ...s DMA read cycle DMA write cycle DMA read cycle DMA write cycle B RD LHWR LLWR TEND Bus released Bus released Bus released Bus released Last transfer cycle Figure 7 24 Example of Transfer in Normal Tr...

Page 222: ...in Normal Transfer Mode by Cycle Stealing Transfer Source DSAR Odd Address and Source Address Increment DMA word read cycle DMA byte write cycle DMA word read cycle Address bus DMA byte write cycle D...

Page 223: ...r is completed In figure 7 27 the TEND signal output is enabled and data is transferred in words from the external 16 bit 2 state access space to the external 16 bit 2 state access space in normal tra...

Page 224: ...s transferred in words from the external 16 bit 2 state access space to the external 16 bit 2 state access space in block transfer mode DMA read cycle DMA read cycle DMA write cycle Address bus DMA wr...

Page 225: ...ion of transfer request disabled Min of 3 cycles Min of 3 cycles Transfer source Transfer destination Transfer destination Transfer source Read Write Read Write Bus released Bus released Bus released...

Page 226: ...urce Transfer destination Transfer destination Transfer source Read Write Read Write Bus released DMA read cycle DMA write cycle DMA read cycle DMA write cycle B DREQ Address bus DMA operation Channel...

Page 227: ...estination Transfer source Read Write Read Write Bus released Bus released Bus released DMA read cycle DMA write cycle DMA read cycle DMA write cycle B DREQ Address bus DMA operation Channel 1 2 3 4 5...

Page 228: ...Transfer source Transfer destination Transfer destination Transfer source Bus released Bus released Bus released DMA read cycle DMA read cycle DMA read cycle DMA read cycle B DREQ Address bus Channel...

Page 229: ...cycle or more by the CPU are executed in the bus released cycles In figure 7 33 the TEND signal output is enabled and data is transferred in bytes from the external 8 bit 2 state access space to the e...

Page 230: ...executed in the bus released cycles In figure 7 34 the TEND signal output is enabled and data is transferred in bytes from the external 8 bit 2 state access space to the external device in single addr...

Page 231: ...cycles Transfer source Transfer destination Single Bus released Bus released Bus released DMA single cycle DMA single cycle B DREQ Address bus DMA operation Channel 1 2 3 4 5 6 7 Transfer request enab...

Page 232: ...les Min of 3 cycles Transfer source Transfer destination Single Bus released Bus released Bus released DMA single cycle DMA single cycle B DREQ Address bus DMA operation Channel 1 2 3 4 5 6 7 Transfer...

Page 233: ...pleted Min of 3 cycles Min of 3 cycles DMA single cycle DMA single cycle B DREQ Address bus Channel 1 2 3 4 5 6 7 1 After DMA transfer request is enabled a low level of the DREQ signal is detected at...

Page 234: ...access size In block transfer mode when the next transfer is requested while a transfer is disabled due to the DTCR value less than the block size When the TSEIE bit in DMDR is cleared to 0 data is t...

Page 235: ...the current DMA cycle and a DMA cycle in which the transfer request is accepted are completed In block transfer mode a DMA transfer is completed after 1 block data is transferred 6 Transfer End by NMI...

Page 236: ...tion 5 7 CPU Priority Control Function Over DMAC The priority level of the DMAC is specified by bits DMAP2 to DMAP0 and can be specified for each channel The priority level of the CPU is specified by...

Page 237: ...is passed to another channel or an auto request transfer by cycle stealing bus cycles of the DMAC and on chip bus master are performed alternatively When the arbitration function among the DMAC and on...

Page 238: ...hannel 1 repeat size end Interrupt by channel 1 extended repeat area overflow on source address Interrupt by channel 1 extended repeat area overflow on destination address DMEEND2 Interrupt by channel...

Page 239: ...e next transfer cannot be performed because the DTCR value is less than the data access size meaning that the data access size of transfers cannot be performed In block transfer mode the block size is...

Page 240: ...ocessing end Transfer resumed after interrupt handling routine DTIF and ESIF bits are cleared to 0 Interrupt handling routine ends DTE bit is set to 1 Registers are specified Transfer resume processin...

Page 241: ...Disable them before entering the module stop state if necessary TENDE bit in DMDR is 1 the TEND signal output enabled DACKE bit in DMDR is 1 the DACK signal output enabled 3 Activation by DREQ Falling...

Page 242: ...Section 7 DMA Controller DMAC Rev 3 00 Mar 14 2006 Page 204 of 804 REJ09B0104 0300 Downloaded from Elcodis com electronic components distributor...

Page 243: ...ols the on off state of the input pull up MOSs Port 2 includes an open drain control register ODR that controls on off of the output buffer PMOSs Ports 1 2 3 6 A D H J and K can drive a single TTL loa...

Page 244: ...SSU I Os 1 P21 TIOCA3 SCS2 IRQ9 A P21 TIOCA3 IRQ9 A 0 P20 TIOCB3 TIOCA3 IRQ8 A P20 TIOCA3 TIOCB3 IRQ8 A Port 3 7 P37 TIOCB2 TIOCA2 TCLKD PO15 P37 TIOCA2 TIOCB2 TCLKD 6 P36 TIOCA2 PO14 P36 TIOCA2 Gener...

Page 245: ...AN6 General I O port also functioning as A D converter inputs 5 P55 AN5 4 P54 AN4 3 P53 AN3 2 P52 AN2 1 P51 AN1 0 P50 AN0 Port 6 6 P66 IRQ14 IRQ14 5 P65 IRQ13 HRxD IRQ13 4 P64 IRQ12 HTxD IRQ12 General...

Page 246: ...ly for SSU 4 PD4 SSO1 3 PD3 SCS0 2 PD2 SSCK0 1 PD1 SSI0 0 PD0 SSO0 7 PH7 O Port H 6 PH6 5 PH5 General I O port 4 PH4 3 PH3 2 PH2 1 PH1 0 PH0 Port J General I O port also functioning as TPU I Os 7 PJ7...

Page 247: ...OCA6 PJ0 TIOCA6 Port K General I O port also functioning as TPU I Os 7 PK7 TIOCB11 TIOCA11 PK7 TIOCA11 TIOCB11 O 6 PK6 TIOCA11 PK6 TIOCA11 5 PK5 TIOCB10 TIOCA10 PK5 TIOCA10 TIOCB10 4 PK4 TIOCA10 PK4 T...

Page 248: ...O O O O Port D 8 O O O O O Port H 8 O O O O O O Port J 8 O O O O O Port K 8 O O O O O Legend O Register exists No register exists Notes 1 The lower four bits are valid and the upper four bits are rese...

Page 249: ...nternal bus To on chip Peripheral module Input buffer Legend WDDR DDR write WDR DR write WICR ICR write WPCR PCR write WODR ODR write RDR DR read RPOR PORT read RICR ICR read RPCR PCR read RODR ODR re...

Page 250: ...6DDR The upper seven bits are valid and the lower one bit is reserved for port A data direction register PADDR 7 Pn7DDR 0 W 6 Pn6DDR 0 W 5 Pn5DDR 0 W 4 Pn4DDR 0 W 3 Pn3DDR 0 W 0 Pn0DDR 0 W 2 Pn2DDR 0...

Page 251: ...1 to 6 A D H J and K ICR is an 8 bit readable writable register that controls the port input buffers For bits in ICR set to 1 the input buffers of the corresponding pins are valid For bits in ICR clea...

Page 252: ...1 while the pin is in input state the input pull up MOS corresponding to the bit in PCR is turned on Table 8 3 shows the input pull up MOS status The initial value of PCR is H 00 7 Pn7PCR 0 R W 6 Pn6...

Page 253: ...Pn7ODR 0 R W 6 Pn6ODR 0 R W 5 Pn5ODR 0 R W 4 Pn4ODR 0 R W 3 Pn3ODR 0 R W 0 Pn0ODR 0 R W 2 Pn2ODR 0 R W 1 Pn1ODR 0 R W Bit Bit Name Initial Value R W 8 1 7 Port H Realtime Input Data Register PHRTIDR P...

Page 254: ...peripheral module pin is followed by A or B the pin function can be modified by the port function control register PFCR For details see section 8 3 3 Port Function Control Register B PFCRB 8 2 1 Port...

Page 255: ...ction is switched as shown below according to the combination of the SCI_3 and P14DDR bit settings Setting SCI_4 I O Port Module Name Pin Function TxD3_OE P14DDR SCI_3 TxD3 output 1 I O port P14 outpu...

Page 256: ...setting 0 7 P11 IRQ1 The pin function is switched as shown below according to the P11DDR bit setting Setting I O Port Module Name Pin Function P11DDR I O port P11 output 1 P11 input initial setting 0...

Page 257: ...DR TPU_3 TIOCD3 output 1 I O port P23 output 0 1 P23 input initial setting 0 0 Note Supported only by the H8SX 1527 2 P22 TIOCC3 IRQ10 A The pin function is switched as shown below according to the co...

Page 258: ...output 1 TPU_3 TIOCA3 output 0 1 I O port P21 output 0 0 1 P21 input initial setting 0 0 0 Note Supported only by the H8SX 1527 4 P20 TIOCA3 TIOCB3 IRQ8 A The pin function is switched as shown below a...

Page 259: ...t 1 PPG PO15 output 0 1 I O port P37 output 0 0 1 P37 input initial setting 0 0 0 Note Supported only by the H8SX 1527 2 P36 PO14 TIOCA2 The pin function is switched as shown below according to the co...

Page 260: ...PO13 output 0 1 P35 output 0 0 1 I O port P35 input initial setting 0 0 0 Note Supported only by the H8SX 1527 4 P34 PO12 TIOCA1 The pin function is switched as shown below according to the combinati...

Page 261: ...11 output 0 1 P33 output 0 0 1 I O port P33 input initial setting 0 0 0 Note Supported only by the H8SX 1527 6 P32 PO10 TIOCC0 TCLKA The pin function is switched as shown below according to the combin...

Page 262: ...O9 output 0 1 P31 output 0 0 1 I O port P31 input initial setting 0 0 0 Note Supported only by the H8SX 1527 8 P30 PO8 TIOCA0 The pin function is switched as shown below according to the combination o...

Page 263: ...pin function is switched as shown below according to the P65DDR bit setting Setting I O Port Module Name Pin Function P65DDR P65 output 1 I O port P65 input initial setting 0 3 P64 IRQ12 HTxD The pin...

Page 264: ...nction is switched as shown below according to the combination of the SCI_4 and P62DDR bit settings Setting SCI_4 I O Port Module Name Pin Function SCK4_OE P62DDR SCI_4 SCK4 output 1 I O port P62 outp...

Page 265: ...rt P60 output 0 1 P60 input initial setting 0 0 8 2 5 Port A 1 PA7 The pin function is switched as shown below according to the PA7DDR bit setting Setting I O Port Module Name Pin Function PA7DDR I O...

Page 266: ...n is switched as shown below according to the PA4DDR bit setting Setting I O Port Module Name Pin Function PA4DDR I O port PA4 output 1 PA4 input initial setting 0 5 PA3 SSO2 The pin function is switc...

Page 267: ...e Pin Function SSI2_OE PA2DDR SSU_2 SSI2 output 1 I O port PA2 output 0 1 PA2 input initial setting 0 0 7 PA1 SSCK2 The pin function is switched as shown below according to the combination of the SSU_...

Page 268: ...function is switched as shown below according to the combination of the SSU_1 and the PD6DDR bit settings Setting SSU_1 I O Port Module Name Pin Function SSCK1_OE PD6DDR SSU_1 SSCK1 output 1 I O port...

Page 269: ...is switched as shown below according to the combination of the SSU_0 and the PD3DDR bit settings Setting SSU_0 I O Port Module Name Pin Function SCS0_OE PD3DDR SSU_0 SCS0 output 1 I O port PD3 output...

Page 270: ...ame Pin Function SSI0_OE PD1DDR SSU_0 SSI0 output 1 I O port PD1 output 0 1 PD1 input initial setting 0 0 8 PD0 SSO0 The pin function is switched as shown below according to the combination of the SSU...

Page 271: ...The pin function is switched as shown below according to the PHnDDR bit setting Setting I O Port Module Name Pin Function PHnDDR I O port PHn output 1 PHn input initial setting 0 Legend n 7 to 0 8 2 8...

Page 272: ...ed as shown below according to the combination of the port function control register A PFCRA TPU_7 and PJ5DDR bit settings Setting TPU_7 I O Port Module Name Pin Function TIOCB7_OE PJ5DDR TPU_7 TIOCB7...

Page 273: ...d as shown below according to the combination of the port function control register A PFCRA TPU_6 and PJ2DDR bit settings Setting TPU_6 I O Port Module Name Pin Function TIOCC6_OE PJ2DDR TPU_6 TIOCC6...

Page 274: ...d as shown below according to the combination of the port function control register A PFCRA TPU_11 and PK7DDR bit settings Setting TPU_11 I O Port Module Name Pin Function TIOCB11_OE PK7DDR TPU_11 TIO...

Page 275: ...shown below according to the combination of the port function control register A PFCRA TPU_10 and PK4DDR bit settings Setting TPU_10 I O Port Module Name Pin Function TIOCA10_OE PK4DDR TPU_10 TIOCA10...

Page 276: ...as shown below according to the combination of the port function control register A PFCRA TPU_9 and PK1DDR bit settings Setting TPU_9 I O Port Module Name Pin Function TIOCB9_OE PK1DDR TPU_9 TIOCB9 ou...

Page 277: ...SU SSCRH_2 CSS0 1 while SSU SSCRL_2 SSUMS 0 SSU SSCRH_2 MSS 1 TIOCA3_OE TIOCA3 TPU TIORH_3 IOA3 0 TPU TIORH_3 IOA 1 0 01 10 11 0 TIOCB3_OE TIOCB3 TPU TIORH_3 IOB3 0 TPU TIORH_3 IOB 1 0 01 10 11 P3 7 T...

Page 278: ...4 SCR TE 1 PA 7 B _OE B PADDR PA7DDR 1 SCKCR PSTOP1 0 SCKCR POSEL1 0 3 SSO2_OE SSI02 When SSU SSCRL_2 SSUMS 0 SSU SSCRH_2 MSS 1 SSU SSCRH_2 BIDE 0 SSU SSER_2 TE 1 or SSU SSCRH_2 BIDE 1 SSU SSER_2 RE 0...

Page 279: ..._0 BIDE 0 SSU SSER_0 TE 1 0 SSO0_OE SSO0 When SSU SSCRL_0 SSUMS 0 SSU SSCRH_0 MSS 1 SSU SSCRH_0 BIDE 0 SSU SSER_0 TE 1 or SSU SSCRH_0 BIDE 1 SSU SSER_0 RE 0 SSU SSER_0 TE 1 When SSU SSCRL_0 SSUMS 0 SS...

Page 280: ...TIOCB10_OE TIOCB10 TPU TIOR_10 IOB3 0 TPU TIOR_10 IOB 1 0 01 10 11 4 TIOCA10_OE TIOCA10 TPU TIOR_10 IOA3 0 TPU TIOR_10 IOA 1 0 01 10 11 3 TIOCD9_OE TIOCD9 TPU TMDR_9 BFB 0 TPU TIORL_9 IOD3 0 TPU TIOR...

Page 281: ...3A 0 R W 4 TPUMS3B 0 R W 3 TPUMS2 0 R W 0 TPUMS0B 0 R W 2 TPUMS1 0 R W 1 TPUMS0A 0 R W Bit Bit Name Initial Value R W Bit Bit Name Initial Value R W Description 7 6 All 0 R W Reserved These bits are a...

Page 282: ...n 0 Specifies P34 as output compare output and input capture 1 Specifies P35 as input capture input and P34 as output compare 1 TPUMS0A 0 R W TPU I O Pin Multiplex Function Select Selects TIOCA0 funct...

Page 283: ...ifies PK7 as input capture input and PK6 as output compare 6 TPUMS10 0 R W TPU I O Pin Multiplex Function Select Selects TIOCA10 function 0 Specifies PK4 as output compare output and input capture 1 S...

Page 284: ...n 0 Specifies PJ4 as output compare output and input capture 1 Specifies PJ5 as input capture input and PJ4 as output compare 1 TPUMS6A 0 R W TPU I O Pin Multiplex Function Select Selects TIOCA6 funct...

Page 285: ...e 0 6 ITS14 0 R W IRQ14 Pin Select Selects an input pin for IRQ14 0 Pin P66 must not be used as IRQ14 A input 1 Pin P66 is used as IRQ14 B input 5 ITS13 0 R W IRQ13 Pin Select Selects an input pin for...

Page 286: ...n P22 is used as IRQ10 A input 1 Pin P62 is used as IRQ10 B input 1 ITS9 0 R W IRQ9 Pin Select Selects an input pin for IRQ9 0 Pin P21 is used as IRQ9 A input 1 Pin P61 is used as IRQ9 B input 0 ITS8...

Page 287: ...ed To use the pin as an output disable the input function for the pin by setting ICR 8 4 2 Notes on Port Function Control Register PFCR Settings The PFC controls I O ports To specify the function of e...

Page 288: ...Section 8 I O Ports Rev 3 00 Mar 14 2006 Page 250 of 804 REJ09B0104 0300 Downloaded from Elcodis com electronic components distributor...

Page 289: ...e set for each channel Waveform output at compare match Input capture function Counter clear operation Synchronous operations Multiple timer counters TCNT can be written to simultaneously Simultaneous...

Page 290: ...16 P 64 P 1024 TCLKA TCLKB TCLKC P 1 P 4 P 16 P 64 P 256 P 1024 P 4096 TCLKA P 1 P 4 P 16 P 64 P 1024 TCLKA TCLKC P 1 P 4 P 16 P 64 P 256 TCLKA TCLKC TCLKD General registers TGR TGRA_0 TGRB_0 TGRA_1 T...

Page 291: ...re Interrupt sources 5 sources Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow 4 sources Compare match...

Page 292: ...6 TIOCA7 TIOCB7 TIOCA8 TIOCB8 TIOCA9 TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10 TIOCA11 TIOCB11 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match...

Page 293: ...tch or input capture 7B Overflow Underflow 4 sources Compare match or input capture 8A Compare match or input capture 8B Overflow Underflow 5 sources Compare match or input capture 9A Compare match or...

Page 294: ...l 1 Channel 2 Internal data bus A D conversion start request signal PPG output trigger signal TIORL Module data bus TGI3A TGI3B TGI3C TGI3D TCI3V TGI4A TGI4B TCI4V TCI4U TGI5A TGI5B TCI5V TCI5U TGI0A...

Page 295: ...TIOCD6 TIOCA7 TIOCB7 TIOCA8 TIOCB8 Interrupt request signals Channel 9 Channel 10 Channel 11 Interrupt request signals Channel 6 Channel 7 Channel 8 Internal data bus TIORL Module data bus TGI9A TGI9...

Page 296: ...t capture input output compare output PWM output pin 1 TIOCA1 I O TGRA_1 input capture input output compare output PWM output pin TIOCB1 I O TGRB_1 input capture input output compare output PWM output...

Page 297: ...output compare output PWM output pin TIOCB7 I O TGRB_7 input capture input output compare output PWM output pin 8 TIOCA8 I O TGRA_8 input capture input output compare output PWM output pin TIOCB8 I O...

Page 298: ...ntrol register H_0 TIORH_0 Timer I O control register L_0 TIORL_0 Timer interrupt enable register_0 TIER_0 Timer status register_0 TSR_0 Timer counter_0 TCNT_0 Timer general register A_0 TGRA_0 Timer...

Page 299: ...I O control register H_3 TIORH_3 Timer I O control register L_3 TIORL_3 Timer interrupt enable register_3 TIER_3 Timer status register_3 TSR_3 Timer counter_3 TCNT_3 Timer general register A_3 TGRA_3...

Page 300: ...egister B_5 TGRB_5 Common Registers Timer start register TSTR Timer synchronous register TSYR Unit 1 Channel 6 Timer control register_6 TCR_6 Timer mode register_6 TMDR_6 Timer I O control register H_...

Page 301: ...r I O control register_8 TIOR_8 Timer interrupt enable register_8 TIER_8 Timer status register_8 TSR_8 Timer counter_8 TCNT_8 Timer general register A_8 TGRA_8 Timer general register B_8 TGRB_8 Channe...

Page 302: ...T_10 Timer general register A_10 TGRA_10 Timer general register B_10 TGRB_10 Channel 11 Timer control register_11 TCR_11 Timer mode register_11 TMDR_11 Timer I O control register_11 TIOR_11 Timer inte...

Page 303: ...input clock edge For details see table 9 7 When the input clock is counted using both edges the input clock period is halved e g P 4 both edges P 2 rising edge If phase counting mode is used on channe...

Page 304: ...earing synchronous operation 1 Notes 1 Synchronous operation is selected by setting the SYNC bit in TSYR to 1 2 When TGRC or TGRD is used as a buffer register TCNT is not cleared because the buffer re...

Page 305: ...16 0 1 1 Internal clock counts on P 64 1 0 0 External clock counts on TCLKA pin input 1 0 1 External clock counts on TCLKB pin input 1 1 0 External clock counts on TCLKC pin input 0 1 1 1 External clo...

Page 306: ...t 1 1 0 External clock counts on TCLKC pin input 2 1 1 1 Internal clock counts on P 1024 Note This setting is ignored when channel 2 is in phase counting mode Table 9 11 TPSC2 to TPSC0 Channel 3 Chann...

Page 307: ...1 1 1 Counts on TCNT5 overflow underflow Note This setting is ignored when channel 4 is in phase counting mode Table 9 13 TPSC2 to TPSC0 Channel 5 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Descript...

Page 308: ...register TGRD input capture output compare is not generated In channels 1 2 4 and 5 which have no TGRD bit 5 is reserved It is a read only bit and cannot be modified 0 TGRB operates normally 1 TGRB a...

Page 309: ...1 0 PWM mode 1 0 0 1 1 PWM mode 2 0 1 0 0 Phase counting mode 1 0 1 0 1 Phase counting mode 2 0 1 1 0 Phase counting mode 3 0 1 1 1 Phase counting mode 4 1 X X X Legend X Don t care Notes 1 MD3 is a...

Page 310: ...RC or TGRD is designated for buffer operation this setting is invalid and the register operates as a buffer register To designate the input capture pin in TIOR the DDR bit and ICR bit for the correspo...

Page 311: ...A3 IOA2 IOA1 IOA0 0 0 0 0 R W R W R W R W I O Control A3 to A0 Specify the function of TGRA For details see tables 9 23 9 25 9 26 9 27 9 29 and 9 30 TIORL_0 TIORL_3 Bit Bit Name Initial Value R W Desc...

Page 312: ...l output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCB0 pin Input capture at ris...

Page 313: ...nitial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCD0 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCD0 pin Input capture at falling edg...

Page 314: ...1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at comp...

Page 315: ...gle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare reg...

Page 316: ...l output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCB3 pin Input capture at ris...

Page 317: ...nitial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCD3 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCD3 pin Input capture at falling edg...

Page 318: ...l output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1...

Page 319: ...gle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare reg...

Page 320: ...t is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 1 Capture input source is TIOCA0 pin Input capture at rising edg...

Page 321: ...output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCC0 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCC0 pin Input capture at falling edge 1 0 1...

Page 322: ...put is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0...

Page 323: ...gle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare reg...

Page 324: ...t is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCA3 pin Input capture at rising edg...

Page 325: ...output is 1 output Toggle output at compare match 1 0 0 0 Capture input source is TIOCC3 pin Input capture at rising edge 1 0 0 1 Capture input source is TIOCC3 pin Input capture at falling edge 1 0 1...

Page 326: ...l output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 1...

Page 327: ...gle output at compare match 0 1 0 0 Output disabled 0 1 0 1 Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare reg...

Page 328: ...ersion start requests by TGRA input capture compare match 0 A D conversion start request generation disabled 1 A D conversion start request generation enabled 6 1 R Reserved This is a read only bit an...

Page 329: ...s 0 and 3 In channels 1 2 4 and 5 bit 2 is reserved It is a read only bit and cannot be modified 0 Interrupt requests TGIC by TGFC bit disabled 1 Interrupt requests TGIC by TGFC bit enabled 1 TGIEB 0...

Page 330: ...annels 0 and 3 bit 7 is reserved It is a read only bit and cannot be modified 0 TCNT counts down 1 TCNT counts up 6 1 R Reserved This is a read only bit and cannot be modified 5 TCFU 0 R W Underflow F...

Page 331: ...3 TGFD 0 R W Input Capture Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3 In channels 1 2 4 and 5 bit 3 is reserved It is a...

Page 332: ...en 0 is written to TGFC after reading TGFC 1 When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled be sure to read the flag after writing 0 to it 1 TGFB 0 R...

Page 333: ...compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register Clearing conditions When DMAC is activated by a TGIA interrupt whil...

Page 334: ...er General Register TGR TGR is a 16 bit readable writable register with a dual function as output compare and input capture registers The TPU has 16 TGR registers four each for channels 0 and 3 and tw...

Page 335: ...served These bits are always read as 0 The write value should always be 0 5 4 3 2 1 0 CST5 CST4 CST3 CST2 CST1 CST0 0 0 0 0 0 0 R W R W R W R W R W R W Counter Start 5 to 0 These bits select operation...

Page 336: ...C1 SYNC0 0 0 0 0 0 0 R W R W R W R W R W R W Timer Synchronization 5 to 0 These bits select whether operation is independent of or synchronized with other channels When synchronous operation is select...

Page 337: ...f the count operation setting procedure Select counter clock Operation selection Select counter clearing source Periodic counter Set period Start count Periodic counter 1 2 4 3 5 Free running counter...

Page 338: ...0 CST bit TCFV Time Figure 9 4 Free Running Counter Operation When compare match is selected as the TCNT clearing source the TCNT counter for the relevant channel performs periodic count operation The...

Page 339: ...compare match cannot be output a Example of setting procedure for waveform output by compare match Figure 9 6 shows an example of the setting procedure for waveform output by a compare match Select wa...

Page 340: ...ue H FFFF H 0000 TIOCA TIOCB Time TGRA TGRB No change No change No change No change 1 output 0 output Figure 9 7 Example of 0 Output 1 Output Operation Figure 9 8 shows an example of toggle output In...

Page 341: ...and 3 P 1 should not be selected as the counter input clock used for input capture input Input capture will not be generated if P 1 is selected a Example of setting procedure for input capture operat...

Page 342: ...ted as the TIOCA pin input capture input edge falling edge has been selected as the TIOCB pin input capture input edge and counter clearing by TGRB input capture has been designated for TCNT TCNT valu...

Page 343: ...resetting 1 2 Synchronous clearing Select counter clearing source Counter clearing 3 Start count 5 Set synchronous counter clearing Synchronous clearing 4 Start count 5 Clearing source generation chan...

Page 344: ...nel 1 and 2 counter clearing source Three phase PWM waveforms are output from pins TIOCA0 TIOCA1 and TIOCA2 At this time synchronous presetting and synchronous clearing by TGRB_0 compare match are per...

Page 345: ...sed in buffer operation Table 9 31 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register TGRA_0 TGRC_0 0 TGRB_0 TGRD_0 TGRA_3 TGRC_3 3 TGRB_3 TGRD_3 When TGR is an o...

Page 346: ...e 9 14 Input Capture Buffer Operation 1 Example of Buffer Operation Setting Procedure Figure 9 15 shows an example of the buffer operation setting procedure Select TGR function Buffer operation Set bu...

Page 347: ...h B 1 output at compare match A and 0 output at compare match B As buffer operation has been set when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously...

Page 348: ...GRA input capture has been set for TCNT and both rising and falling edges have been selected as the TIOCA pin input capture input edge As buffer operation has been set when the TCNT value is stored in...

Page 349: ...4 the counter clock setting is invalid and the counter operates independently in phase counting mode Table 9 32 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT_1 TC...

Page 350: ...are transferred to TGRA_1 and the lower 16 bits to TGRA_2 TCNT_2 clock TCNT_2 H FFFF H 0000 H 0001 TIOCA1 TIOCA2 TGRA_1 H 03A2 TGRA_2 H 0000 TCNT_1 clock TCNT_1 H 03A1 H 03A2 Figure 9 19 Example of C...

Page 351: ...ration is also possible There are two PWM modes as described below 1 PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD The outputs specified...

Page 352: ...PWM mode 2 a maximum 15 phase PWM output is possible by combined use with synchronous operation The correspondence between PWM output pins and registers is shown in table 9 33 Table 9 33 PWM Output R...

Page 353: ...e 3 Use TIOR to designate TGR as an output compare register and select the initial value and output value 4 Set the cycle in TGR selected in 2 and set the duty in the other TGRs 5 Select the PWM mode...

Page 354: ...match is set as the TCNT clearing source and 0 is set for the initial output value and 1 for the output value of the other TGR registers TGRA_0 to TGRD_0 TGRA_1 to output a 5 phase PWM waveform In thi...

Page 355: ...lue TGRA H 0000 TIOCA Time TGRB 100 duty TGRB changed TGRB changed TGRB changed Output does not change when compare matches in cycle register and duty register occur simultaneously TCNT value TGRA H 0...

Page 356: ...IER and TGR are valid and input capture compare match and interrupt functions can be used This can be used for two phase encoder pulse input When overflow occurs while TCNT is counting up the TCFV fla...

Page 357: ...of the phase counting mode setting procedure Phase counting mode Select phase counting mode Start count Phase counting mode Select phase counting mode with bits MD3 to MD0 in TMDR Set the CST bit in...

Page 358: ...9 35 summarizes the TCNT up down count conditions TCNT value Time Down count Up count TCLKA channels 1 and 5 TCLKC channels 2 and 4 TCLKB channels 1 and 5 TCLKD channels 2 and 4 Figure 9 26 Example o...

Page 359: ...KB channels 1 and 5 TCLKD channels 2 and 4 Figure 9 27 Example of Phase Counting Mode 2 Operation Table 9 36 Up Down Count Conditions in Phase Counting Mode 2 TCLKA Channels 1 and 5 TCLKC Channels 2 a...

Page 360: ...KB channels 1 and 5 TCLKD channels 2 and 4 Figure 9 28 Example of Phase Counting Mode 3 Operation Table 9 37 Up Down Count Conditions in Phase Counting Mode 3 TCLKA Channels 1 and 5 TCLKC Channels 2 a...

Page 361: ...C channels 2 and 4 TCLKB channels 1 and 5 TCLKD channels 2 and 4 Figure 9 29 Example of Phase Counting Mode 4 Operation Table 9 38 Up Down Count Conditions in Phase Counting Mode 4 TCLKA Channels 1 an...

Page 362: ...match TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control cycle and position control cycle TGRB_0 is used for input capture with TGRB_0 and TGRD_0 operating i...

Page 363: ..._1 speed cycle capture TGRA_0 speed control cycle TGRB_1 position cycle capture TGRC_0 position control cycle TGRB_0 pulse width capture TGRD_0 buffer operation Channel 0 TCLKA TCLKB Edge detection ci...

Page 364: ...l is fixed For details see section 5 Interrupt Controller Table 9 39 lists the TPU interrupt sources Table 9 39 TPU Interrupts Channel Name Interrupt Source Interrupt Flag DMAC Activation 0 TGI0A TGRA...

Page 365: ...le 6 TGI6A TGRA_0 input capture compare match TGFA_0 Possible TGI6B TGRB_0 input capture compare match TGFB_0 Not possible TGI6C TGRC_0 input capture compare match TGFC_0 Not possible TGI6D TGRD_0 inp...

Page 366: ...Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture compare match on a channel The interrupt request i...

Page 367: ...activate the A D converter this function is not available for unit 1 If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture compare match...

Page 368: ...n and figure 9 32 shows TCNT count timing in external clock operation P Internal clock TCNT input clock TCNT Falling edge Rising edge N 1 N 1 N 2 N Falling edge Figure 9 31 Count Timing in Internal Cl...

Page 369: ...tput compare output pin TIOC pin After a match between TCNT and TGR the compare match signal is not generated until the TCNT input clock is generated Figure 9 33 shows output compare output timing P T...

Page 370: ...e match occurrence is specified and figure 9 36 shows the timing when counter clearing by input capture occurrence is specified P TCNT N TGR Compare match signal Counter clear signal H 0000 N Figure 9...

Page 371: ...d 9 38 show the timings in buffer operation P n 1 n TGRA TGRB TGRC TGRD N N Compare match signal TCNT n Figure 9 37 Buffer Operation Timing Compare Match P TCNT N 1 N Input capture signal TGRA TGRB TG...

Page 372: ...ignal timing TGR Compare match signal P TCNT input clock TCNT N 1 N N TGF flag TGI interrupt Figure 9 39 TGI Interrupt Timing Compare Match 2 TGF Flag Setting Timing in Case of Input Capture Figure 9...

Page 373: ...g Figure 9 42 shows the timing for setting of the TCFU flag in TSR by underflow occurrence and the TCIU interrupt request signal timing H FFFF P TCNT input clock TCNT overflow Overflow signal TCFV fla...

Page 374: ...cleared in synchronization with P after the DMAC transfer has started as shown in figure 9 44 If conflict occurs for clearing the status flag and interrupt request signal due to activation of multiple...

Page 375: ...r details refer to section 19 Power Down Modes 9 9 2 Input Clock Restrictions The input clock pulse width must be at least 1 5 states in the case of single edge detection and at least 2 5 states in th...

Page 376: ...n by the following formula f P N 1 f P N Counter frequency Operating frequency TGR set value 9 9 4 Conflict between TCNT Write and Clear Operations If the counter clearing signal is generated in the T...

Page 377: ...ss Figure 9 48 Conflict between TCNT Write and Increment Operations 9 9 6 Conflict between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle the TGR write take...

Page 378: ...le Buffer register address Data written to buffer register M Buffer register Figure 9 50 Conflict between Buffer Register Write and Compare Match 9 9 8 Conflict between TGR Read and Input Capture If t...

Page 379: ...ycle M M TGR Figure 9 52 Conflict between TGR Write and Input Capture 9 9 10 Conflict between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buff...

Page 380: ...TCNT input clock TCNT TGF flag TCFV flag H FFFF Disabled Figure 9 54 Conflict between Overflow and Counter Clearing 9 9 12 Conflict between TCNT Write and Overflow Underflow If an overflow underflow...

Page 381: ...n and the TCLKD input pin with the TIOCB2 I O pin When an external clock is input compare match output should not be performed from a multiplexed pin 9 9 14 Interrupts and Module Stop Mode If module s...

Page 382: ...Section 9 16 Bit Timer Pulse Unit TPU Rev 3 00 Mar 14 2006 Page 344 of 804 REJ09B0104 0300 Downloaded from Elcodis com electronic components distributor...

Page 383: ...s Non overlapping mode Can operate together with the DMA controller DMAC Inverted output can be set Module stop mode can be set Compare match signals PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Legend PMR P...

Page 384: ...t Output Pins Table 10 1 shows the PPG pin configuration Table 10 1 Pin Configuration Pin Name I O Function PO15 Output PO14 Output PO13 Output PO12 Output Group 3 pulse output PO11 Output PO10 Output...

Page 385: ...G output control register PCR PPG output mode register PMR 10 3 1 Next Data Enable Registers H L NDERH NDERL NDERH and NDERL enable disable pulse output on a bit by bit basis NDERH 7 NDER15 0 R W 6 ND...

Page 386: ...ansferred to the PODRH bit by the selected output trigger Values are not transferred from NDRH to PODRH for cleared bits NDERL Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 NDER7 NDER6 ND...

Page 387: ...0 R W 6 POD6 0 R W 5 POD5 0 R W 4 POD4 0 R W 3 POD3 0 R W 2 POD2 0 R W 1 POD1 0 R W 0 POD0 0 R W Bit Bit Name Initial Value R W PODRH Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 POD15 P...

Page 388: ...e to this register While NDERL is cleared the initial output value of the pulse can be set 10 3 3 Next Data Registers H L NDRH NDRL NDRH and NDRL store the next data for pulse output The NDR addresses...

Page 389: ...ent output triggers the upper four bits and lower four bits are mapped to different addresses as shown below Bit Bit Name Initial Value R W Description 7 6 5 4 NDR15 NDR14 NDR13 NDR12 0 0 0 0 R W R W...

Page 390: ...rent output triggers the upper four bits and lower four bits are mapped to different addresses as shown below Bit Bit Name Initial Value R W Description 7 6 5 4 NDR7 NDR6 NDR5 NDR4 0 0 0 0 R W R W R W...

Page 391: ...1 G3CMS0 1 1 R W R W Group 3 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 3 00 Compare match in TPU channel 0 01 Compare match in TPU channel 1 10 Compare match...

Page 392: ...igger For details refer to section 10 4 4 Non Overlapping Pulse Output 7 G3INV 1 R W 6 G2INV 1 R W 5 1 R W 4 1 R W 3 G3NOV 0 R W 2 G2NOV 0 R W 1 0 R W 0 0 R W Bit Bit Name Initial Value R W Bit Bit Na...

Page 393: ...erlapping operation output values updated at compare match A or B in the selected TPU channel 2 G2NOV 0 R W Group 2 Non Overlap Selects normal or non overlapping operation for pulse output group 2 0 N...

Page 394: ...is possible by writing new output data to NDR before the next compare match Output trigger signal Pulse output pin Internal data bus Normal output inverted output C PODR Q D NDER Q NDR Q D Figure 10...

Page 395: ...output compare register with output disabled 2 Set the PPG output trigger cycle 3 Select the counter clock source with bits TPSC2 to TPSC0 in TCR Select the counter clear source with bits CCLR1 and CC...

Page 396: ...the TGIEA bit in TIER to 1 to enable the compare match input capture A TGIA interrupt 2 Write H F8 to NDERH and set bits G3CMS1 G3CMS0 G2CMS1 and G2CMS0 in PCR to select compare match in the TPU chan...

Page 397: ...ch A Compare match B Pulse output pin Internal data bus Normal output inverted output C PODR Q D NDER Q NDR Q D Figure 10 6 Non Overlapping Pulse Output Therefore 0 data can be transferred ahead of 1...

Page 398: ...this operation 0 1 output 0 output 0 1 output 0 output Do not write to NDR here Write to NDR here Compare match A Compare match B NDR PODR Do not write to NDR here Write to NDR here Write to NDR Write...

Page 399: ...ut disabled 2 Set the pulse output trigger cycle in TGRB and the non overlapping margin in TGRA 3 Select the counter clock source with bits TPSC2 to TPSC0 in TCR Select the counter clear source with b...

Page 400: ...gure 10 9 shows an example in which pulse output is used for 4 phase complementary non overlapping pulse output TCNT value TCNT TGRB TGRA H 0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05...

Page 401: ...output trigger Set bits G3NOV and G2NOV in PMR to 1 to select non overlapping pulse output Write output data H 95 to NDRH 3 The timer counter in the TPU channel starts When a compare match with TGRB o...

Page 402: ...e of the PODR contents can be output Figure 10 10 shows the outputs when the G3INV and G2INV bits are cleared to 0 in addition to the settings of figure 10 9 TCNT value TCNT TGRB TGRA H 0000 NDRH 95 6...

Page 403: ...e Stop Mode Setting PPG operation can be disabled or enabled using the module stop control register The initial value is for PPG operation to be halted Register access is enabled by clearing module st...

Page 404: ...Section 10 Programmable Pulse Generator PPG Rev 3 00 Mar 14 2006 Page 366 of 804 REJ09B0104 0300 Downloaded from Elcodis com electronic components distributor...

Page 405: ...input clocks Switchable between watchdog timer mode and interval timer mode In watchdog timer mode If the counter overflows this LSI can be initialized internally In interval timer mode If the counter...

Page 406: ...mal registers For details see section 11 5 1 Notes on Register Access Timer counter TCNT Timer control status register TCSR Reset control status register RSTCSR 11 2 1 Timer Counter TCNT TCNT is an 8...

Page 407: ...ition When TCNT overflows in interval timer mode changes from H FF to H 00 When internal reset request generation is selected in watchdog timer mode OVF is cleared automatically by the internal reset...

Page 408: ...010 Clock P 128 cycle 1 6 ms 011 Clock P 512 cycle 6 6 ms 100 Clock P 2048 cycle 26 2 ms 101 Clock P 8192 cycle 104 9 ms 110 Clock P 32768 cycle 419 4 ms 111 Clock P 131072 cycle 1 68 s Note Only 0 c...

Page 409: ...dition Reading RSTCSR when WOVF 1 and then writing 0 to WOVF 6 RSTE 0 R W Reset Enable Specifies whether or not this LSI is internally reset if TCNT overflows during watchdog timer operation 0 LSI is...

Page 410: ...signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow TCNT has overflowed the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0 The internal rese...

Page 411: ...me time the OVF bit in the TCSR is set to 1 TCNT value H 00 Time H FF WT IT 0 TME 1 WOVI Overflow Overflow Overflow Overflow WOVI Interval timer interrupt request WOVI WOVI WOVI Figure 11 3 Operation...

Page 412: ...nsfer instruction for address H FFA6 A byte transfer instruction cannot be used to write to RSTCSR The method of writing 0 to the WOVF bit in RSTCSR differs from that of writing to the RSTE bit in RST...

Page 413: ...ignal TCNT input clock TCNT TCNT write cycle Counter write data Figure 11 5 Conflict between TCNT Write and Increment 11 5 3 Changing Values of Bits CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are writt...

Page 414: ...instruction is executed when the SSBY bit in SBYCR is set to 1 Instead a transition to sleep mode is made To transit to software standby mode the SLEEP instruction must be executed after halting the W...

Page 415: ...mode Full duplex communication capability The transmitter and receiver are mutually independent enabling transmission and reception to be executed simultaneously Double buffering is used in both the t...

Page 416: ...and inverse convention are supported RxD TxD SCK Clock P P 4 P 16 P 64 TEI TXI RXI ERI SCMR SSR SCR SMR Transmission reception control Baud rate generator BRR Module data bus RDR TSR RSR Parity gener...

Page 417: ...O Function SCK3 I O Channel 3 clock input output RxD3 Input Channel 3 receive data input 3 TxD3 Output Channel 3 transmit data output SCK4 I O Channel 4 clock input output RxD4 Input Channel 4 receive...

Page 418: ...ing register sections Channel 3 Receive shift register_3 RSR_3 Transmit shift register_3 TSR_3 Receive data register_3 RDR_3 Transmit data register_3 TDR_3 Serial mode register_3 SMR_3 Serial control...

Page 419: ...in SSR is set to 1 read RDR only once RDR cannot be written to by the CPU Bit Bit Name Initial Value R W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R 12 3 3 Transmit Data Register TDR TDR is an 8...

Page 420: ...0 R W 6 CHR 0 R W 5 PE 0 R W 4 O E 0 R W 3 STOP 0 R W 2 MP 0 R W 1 CKS1 0 R W 0 CKS0 0 R W Bit Bit Name Initial Value R W When SMIF in SCMR 1 7 GM 0 R W 6 BLK 0 R W 5 PE 0 R W 4 O E 0 R W 3 BCP1 0 R W...

Page 421: ...the stop bit length in transmission 0 1 stop bit 1 2 stop bits In reception only the first stop bit is checked If the second stop bit is 0 it is treated as the start bit of the next transmit frame 2 M...

Page 422: ...ode When this bit is set to 1 the parity bit is added to transmit data before transmission and the parity bit is checked in reception Set this bit to 1 in smart card interface mode 4 O E 0 R W Parity...

Page 423: ...ementary Time Unit 1 bit transfer time 12 3 6 Serial Control Register SCR SCR is a register that enables disables the following SCI transfer operations and interrupt requests and selects the transfer...

Page 424: ...5 TE 0 R W Transmit Enable When this bit is set to 1 transmission is enabled Under this condition serial transmission is started by writing transmit data to TDR and clearing the TDRE flag in SSR to 0...

Page 425: ...R is set to 1 the MPIE bit is automatically cleared to 0 and RXI and ERI interrupt requests in the case where the TIE and RIE bits in SCR are set to 1 and setting of the FER and ORER flags are enabled...

Page 426: ...writing transmit data to TDR and clearing the TDRE flag in SSR to 0 Note that SMR should be set prior to setting the TE bit to 1 in order to designate the transmission format If transmission is halte...

Page 427: ...ock output 12 3 7 Serial Status Register SSR SSR is a register containing status flags of the SCI and multiprocessor bits for transfer TDRE RDRF ORER PER and FER can only be cleared Some bits in SSR h...

Page 428: ...est is issued allowing DMAC to write data to TDR 6 RDRF 0 R W Receive Data Register Full Indicates whether receive data is stored in RDR Setting condition When serial reception ends normally and recei...

Page 429: ...Even when the RE bit in SCR is cleared the ORER flag is not affected and retains its previous value 4 FER 0 R W Framing Error Indicates that a framing error has occurred during reception in asynchrono...

Page 430: ...CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled be sure to read the flag after writing 0 to it Even when the RE bit in SCR is cleared the PER bit is not affect...

Page 431: ...ssued allowing DMAC to write data to TDR 6 RDRF 0 R W Receive Data Register Full Indicates whether receive data is stored in RDR Setting condition When serial reception ends normally and receive data...

Page 432: ...ormed Note that in clocked synchronous mode serial transmission also cannot continue Clearing condition When 0 is written to ORER after reading ORER 1 When the CPU is used to clear this flag by writin...

Page 433: ...is transferred to RDR however the RDRF flag is not set Note that when the PER flag is being set to 1 the subsequent serial reception cannot be performed In clocked synchronous mode serial transmission...

Page 434: ...depends on the register setting as follows When GM 0 and BLK 0 2 5 etu after transmission start When GM 0 and BLK 1 1 5 etu after transmission start When GM 1 and BLK 0 1 0 etu after transmission sta...

Page 435: ...used for transmission reception when the 7 bit data format is used data is always transmitted received with LSB first 2 SINV 0 R W Smart Card Data Invert Inverts the transmit receive data logic level...

Page 436: ...2 B 2n 1 P 106 Smart card interface mode N 1 S 2 B P 106 2n 1 Error B S 2 N 1 1 100 2n 1 P 106 Legend B Bit rate bit s N BRR setting for baud rate generator 0 N 255 P Operating frequency MHz n and S...

Page 437: ...6 0 31 0 00 0 32 1 36 0 38 0 16 19200 0 12 0 16 0 15 0 00 0 15 1 73 0 19 2 34 31250 0 7 0 00 0 9 1 70 0 9 0 00 0 11 0 00 38400 0 7 0 00 0 7 1 73 0 9 2 34 Operating Frequency P MHz 12 288 14 14 7456 16...

Page 438: ...0 69 0 63 0 00 0 64 0 16 19200 0 27 0 00 0 28 1 02 0 31 0 00 0 32 1 36 31250 0 16 1 20 0 17 0 00 0 19 1 70 0 19 0 00 38400 0 13 0 00 0 14 2 34 0 15 0 00 0 15 1 73 Operating Frequency P MHz 25 30 33 3...

Page 439: ...0 937500 0 0 14 7456 460800 0 0 33 1031250 0 0 16 500000 0 0 35 1093750 0 0 Table 12 5 Maximum Bit Rate with External Clock Input Asynchronous Mode P MHz External Input Clock MHz Maximum Bit Rate bit...

Page 440: ...Hz 8 10 16 20 Bit Rate bit s n N n N n N n N 110 250 3 124 3 249 500 2 249 3 124 1k 2 124 2 249 2 5k 1 199 1 249 2 99 2 124 5k 1 99 1 124 1 199 1 249 10k 0 199 0 249 1 99 1 124 25k 0 79 0 99 0 159 0 1...

Page 441: ...4 1M 2 5M 0 2 5M Legend Space Setting prohibited Can be set but there will be error Continuous transmission or reception is not possible Table 12 7 Maximum Bit Rate with External Clock Input Clocked S...

Page 442: ...rror n N Error 9600 0 1 0 00 0 1 12 01 0 2 15 99 0 2 6 60 Operating Frequency P MHz 25 00 30 00 33 00 35 00 Bit Rate bit s n N Error n N Error n N Error n N Error 9600 0 3 12 49 0 3 5 01 0 4 7 59 0 4...

Page 443: ...nizes a start bit and starts serial communication Inside the SCI the transmitter and receiver are independent units enabling full duplex communication Both the transmitter and the receiver also have a...

Page 444: ...Asynchronous Mode PE 0 0 1 1 0 0 1 1 S 8 bit data STOP S 7 bit data STOP S 8 bit data STOP STOP S 8 bit data P STOP S 7 bit data STOP P S 8 bit data MPB STOP S 8 bit data MPB STOP STOP S 7 bit data ST...

Page 445: ...tion margin in asynchronous mode is determined by formula 1 below M 0 5 L 0 5 F 1 F 100 Formula 1 2N 1 N D 0 5 M Reception margin N Ratio of bit rate to clock N 16 D Duty cycle of clock D 0 5 to 1 0 L...

Page 446: ...al clock is input to the SCK pin the clock frequency should be 16 times the bit rate used When the SCI is operated on an internal clock the clock can be output from the SCK pin The frequency of the cl...

Page 447: ...d CKE0 bits in SCR TE and RE bits are 0 No Yes Set value in BRR Set corresponding bit in ICR to 1 3 4 Set TE or RE bit in SCR to 1 and set RIE TIE TEIE and MPIE bits 5 1 bit interval elapsed 1 Set the...

Page 448: ...ultiprocessor bit may be omitted depending on the format and stop bit 4 The SCI checks the TDRE flag at the timing for sending the stop bit 5 If the TDRE flag is 0 the next transmit data is transferre...

Page 449: ...ansmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial transmission continuation procedure To continue serial transmi...

Page 450: ...to 1 at this time an ERI interrupt request is generated 4 If a framing error when the stop bit is 0 is detected the FER bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in...

Page 451: ...suming reception Figure 12 9 shows a sample flowchart for serial data reception Table 12 11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF ORER FER PER Receive Data Receive Error Type...

Page 452: ...e that the ORER PER and FER flags are all cleared to 0 Reception cannot be resumed if any of these flags are set to 1 In the case of a framing error a break can be detected by reading the value of the...

Page 453: ...rocessing Parity error processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER 1 FER 1 Break PER 1 Clear RE bit in SCR to...

Page 454: ...ation and a multiprocessor bit set to 1 It then transmits transmit data added with the multiprocessor bit cleared to 0 The receiving station skips data until data with the multiprocessor bit set to 1...

Page 455: ...02 ID 03 ID 04 Communication line Serial data ID transmission cycle receiving station specification Data transmission cycle Data transmission to receiving station specified by ID MPB 1 MPB 0 H 01 H A...

Page 456: ...omatically designated as the transmit data output pin After the TE bit is set to 1 a 1 is output for one frame and transmission is enabled 2 SCI status check and transmit data write Read SSR and check...

Page 457: ...t Stop bit Start bit Data Data 2 Stop bit RXI interrupt request multiprocessor interrupt generated Idle state mark state RDRF RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routi...

Page 458: ...SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and compare it with this station s ID If the data is not this station s ID set the MPIE bit to 1 again and clear the RDR...

Page 459: ...Error processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER 1 FER 1 Break Clear RE bit in SCR to 0 5 Figure 12 13 Sample Mult...

Page 460: ...ffered structure so that the next transmit data can be written during transmission or the previous receive data can be read during reception enabling continuous data transfer Don t care Don t care One...

Page 461: ...bit in SCR to 1 and set RIE TIE TEIE and MPIE bits 5 1 bit interval elapsed Set CKE1 and CKE0 bits in SCR TE and RE bits are 0 1 1 Set the bit in ICR for the corresponding pin when receiving data or u...

Page 462: ...from the TxD pin synchronized with the output clock when clock output mode has been specified and synchronized with the input clock when use of an external clock has been specified 4 The SCI checks th...

Page 463: ...Yes Read TEND flag in SSR 3 Clear TE bit in SCR to 0 TDRE 1 All data transmitted TEND 1 1 SCI initialization The TxD pin is automatically designated as the transmit data output pin 2 SCI state check...

Page 464: ...finishes successfully the RDRF bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR is set to 1 at this time an RXI interrupt request is generated Because the RXI inter...

Page 465: ...MSB bit 7 of the current frame is received reading the RDRF flag reading RDR and clearing the RDRF flag to 0 should be finished However the RDRF flag is cleared automatically when the DMAC is initiat...

Page 466: ...RER flag is set to 1 4 SCI state check and receive data read Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and clear the RDRF flag to 0 Transition of the RDRF fla...

Page 467: ...I communicates with the IC card using a single transmission line interconnect the TxD and RxD pins and pull up the data transmission line to VCC using a resistor Setting the RE and TE bits to 1 with t...

Page 468: ...from the start bit If an error signal is sampled during transmission the same data is automatically re transmitted after at least 2 etu Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp In normal transmission reception...

Page 469: ...oth the SDIR and SINV bits in SCMR The parity bit is logic level 0 to produce even parity which is prescribed by the smart card standard and corresponds to state Z Since the SNIV bit of this LSI only...

Page 470: ...d 186th and 128th rising edges of the basic clock so that it can be latched at the middle of each bit as shown in figure 12 25 The reception margin here is determined by the following formula M 0 5 L...

Page 471: ...esponding to the bit rate in BRR 7 Set the CKE1 and CKE0 bits in SCR appropriately Clear the TIE RIE TE RE MPIE and TEIE bits to 0 simultaneously When the CKE0 bit is set to 1 the SCK pin is allowed t...

Page 472: ...E bit in SCR is set to 1 Writing transmit data to TDR starts transmission of the next data Figure 12 28 shows a sample flowchart for transmission All the processing steps are automatically performed u...

Page 473: ...ansfer from TDR to TSR 2 4 3 Figure 12 26 Data Re Transfer Operation in SCI Transmission Mode Note that the TEND flag is set in different timings depending on the GM bit setting in SMR Figure 12 27 sh...

Page 474: ...s Clear TE bit in SCR to 0 Start transmission Start No No No Yes Yes Yes Yes No End Write data to TDR and clear TDRE flag in SSR to 0 Error processing Error processing TEND 1 All data transmitted TEND...

Page 475: ...t to activate the DMAC In reception setting the RIE bit to 1 allows an RXI interrupt request to be generated when the RDRF flag is set to 1 This activates the DMAC by an RXI request thus allowing tran...

Page 476: ...Figure 12 30 Sample Reception Flowchart 12 7 8 Clock Output Control Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1 Specifically the minimum width of...

Page 477: ...data register DR and data direction register DDR corresponding to the SCK pin to the values for the output fixed state in software standby mode 2 Write 0 to the TE and RE bits in SCR to stop transmiss...

Page 478: ...nterrupt request is generated When the ORER PER or FER flag in SSR is set to 1 an ERI interrupt request is generated An RXI interrupt can activate the DMAC to allow data transfer The RDRF flag is auto...

Page 479: ...tomatically re transmits the same data During re transmission the TEND flag remains as 0 thus not activating the DMAC Therefore the SCI and DMAC automatically transmit the specified number of bytes in...

Page 480: ...ction input or output and level are determined by DR and DDR This can be used to set the TxD pin to mark state high level or send a break during serial data transmission To maintain the communication...

Page 481: ...write transmit data to TDR after verifying that the TDRE flag is set to 1 12 9 6 Restrictions on Using DMAC When the external clock source is used as a synchronization clock update TDR by the DMAC and...

Page 482: ...after mode cancellation set the TE bit to 1 read SSR write to TDR clear TDRE in this order and then start transmission To transmit data in a different transmission mode initialize the SCI first Figure...

Page 483: ...ndby mode TE 0 Initialization TE 1 2 3 All data transmitted Change operating mode TEND 1 1 Data being transmitted is lost halfway Data can be normally transmitted from the CPU by setting the TE bit to...

Page 484: ...12 35 Port Pin States during Mode Transition Internal Clock Asynchronous Transmission TE bit SCK output pin TxD output pin Port input output Port input output Port input output High output Marking ou...

Page 485: ...ta in RDR Read RDRF flag in SSR Make transition to software standby mode Cancel software standby mode RE 0 Initialization RE 1 2 Change operating mode RDRF 1 1 Data being received will be invalid 2 Mo...

Page 486: ...Section 12 Serial Communication Interface SCI Rev 3 00 Mar 14 2006 Page 448 of 804 REJ09B0104 0300 Downloaded from Elcodis com electronic components distributor...

Page 487: ...it stuffing function Broadcast communication system Transmission path Bidirectional 2 wire serial communication Communication speed Max 1 Mbps Data length 0 to 8 bytes Number of channels 1 Data buffer...

Page 488: ...register HCAN Bosch CAN 2 0B active Figure 13 1 HCAN Block Diagram Message Buffer Interface MBI The MBI consisting of mailboxes and a local acceptance filter mask LAFM stores CAN transmit receive mess...

Page 489: ...CAN settings In addition when using HCAN pins settings must be made in the HCAN configuration mode during initialization MCR0 1 and GSR3 1 Table 13 1 Pin Configuration Name Abbreviation Input Output F...

Page 490: ...dge register TXACK Abort acknowledge register ABACK Receive complete register RXPR Remote request register RFPR Interrupt register IRR Mailbox interrupt mask register MBIMR Interrupt mask register IMR...

Page 491: ...Reserved This is a read only bit and cannot be modified 5 MCR5 0 R W HCAN Sleep Mode When this bit is set to 1 the HCAN enters HCAN sleep mode When this bit is cleared to 0 HCAN sleep mode is released...

Page 492: ...7 0 R 6 0 R 5 0 R 4 0 R 3 GSR3 1 R 0 GSR0 0 R 2 GSR2 1 R 1 GSR1 0 R Bit Bit Name Initial Value R W Bit Bit Name Initial Value R W Description 7 to 4 All 0 R Reserved These are read only bits and canno...

Page 493: ...ondition Start of message transmission SOF Clearing condition Third bit of Intermission after EOF End of Frame 1 GSR1 0 R Transmit Receive Warning Flag This bit cannot be modified Clearing condition W...

Page 494: ...nitial Value R W Bit Bit Name Initial Value R W Description 15 14 BCR7 BCR6 0 0 R W R W Re Synchronization Jump Width SJW Set the maximum bit synchronization width 00 1 time quantum 01 2 time quanta 1...

Page 495: ...ta 110 7 time quanta 111 8 time quanta 3 2 1 0 BCR11 BCR10 BCR9 BCR8 0 0 0 0 R W R W R W R W Time Segment 1 TSEG1 Set the TSEG1 PRSEG PHSEG1 width to between 4 and 16 time quanta 0000 Setting prohibit...

Page 496: ...ame Initial Value R W Bit Bit Name Initial Value R W Description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8 0...

Page 497: ...ame Initial Value R W Bit Bit Name Initial Value R W Description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8 0...

Page 498: ...Value R W Bit Bit Name Initial Value R W Description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8 0 0 0 0 0 0 0...

Page 499: ...it Name Initial Value R W Description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 0 0 0 0 0 0 0...

Page 500: ...nitial Value R W Description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 0 0 0 0 0 0 0 0 0 0 0...

Page 501: ...4 RXPR12 0 R W 3 RXPR11 0 R W 0 RXPR8 0 R W 2 RXPR10 0 R W 1 RXPR9 0 R W Bit Bit Name Initial Value R W Note Only 1 can be written to these bits to clear the flags Bit Bit Name Initial Value R W Descr...

Page 502: ...PR11 0 R W 0 RFPR8 0 R W 2 RFPR10 0 R W 1 RFPR9 0 R W Bit Bit Name Initial Value R W Note Only 1 can be written to these bits to clear the flags Bit Bit Name Initial Value R W Description 15 14 13 12...

Page 503: ...Bit Name Initial Value R W Note Only 1 can be written to these bits to clear the flags Bit Bit Name Initial Value R W Description 15 IRR7 0 R W Overload Frame Interrupt Flag Status flag indicating th...

Page 504: ...flag indicating the error passive state caused by the transmit receive error counter Setting condition When TEC 128 or REC 128 Clearing condition Writing 1 When the CPU is used to clear this flag by...

Page 505: ...10 IRR2 0 R Remote Frame Request Interrupt Flag When MBIMR 0 Status flag indicating that a remote frame has been received in a mailbox buffer Setting condition When remote frame reception is completed...

Page 506: ...n reset or software standby mode Clearing condition Writing 1 When the CPU is used to clear this flag by writing 1 while the corresponding interrupt is enabled be sure to read the flag after writing 1...

Page 507: ...aring condition Clearing of all bits in UMSR unread message status register 0 IRR8 0 R W Mailbox Empty Interrupt Flag Status flag indicating that the next transmit message can be stored in the mailbox...

Page 508: ...ue R W Bit Bit Name Initial Value R W Description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 M...

Page 509: ...hen this bit is cleared to 0 an interrupt request by IRR7 OVR0 is enabled When set to 1 it is masked 14 IMR6 1 R W Bus Off Interrupt Mask When this bit is cleared to 0 an interrupt request by IRR6 ERS...

Page 510: ...only bit and cannot be modified 7 to 5 All 1 R Reserved These are read only bits and cannot be modified 4 IMR12 1 R W Bus Operation Interrupt Mask When this bit is cleared to 0 an interrupt request b...

Page 511: ...e is stipulated in the CAN protocol 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 0 0 R 2 0 R 1 0 R Bit Bit Name Initial Value R W 13 3 15 Transmit Error Counter TEC TEC functions as a counter indicating the number o...

Page 512: ...SR11 0 R W 0 UMSR8 0 R W 2 UMSR10 0 R W 1 UMSR9 0 R W Bit Bit Name Initial Value R W Note Only 1 can be written to these bits to clear the flags Bit Bit Name Initial Value R W Description 15 14 13 12...

Page 513: ...R W 12 LAFML4 0 R W 11 LAFML3 0 R W 8 LAFML0 0 R W 10 LAFML2 0 R W 9 LAFML1 0 R W Bit Bit Name Initial Value R W 7 LAFML15 0 R W 6 LAFML14 0 R W 5 LAFML13 0 R W 4 LAFML12 0 R W 3 LAFML11 0 R W 0 LAFM...

Page 514: ...ier is not compared When this bit is set to 1 ID 2 of the receive message identifier is not compared When this bit is set to 1 ID 1 of the receive message identifier is not compared When this bit is s...

Page 515: ...s bit is set to 1 ID 17 of the receive message identifier is not compared When this bit is set to 1 ID 16 of the receive message identifier is not compared When this bit is set to 1 ID 28 of the recei...

Page 516: ...15 2 MC0 3 MC1 3 MC2 3 MC3 3 MC15 3 MC0 4 MC1 4 MC2 4 MC3 4 MC15 4 MC0 5 MC1 5 MC2 5 MC3 5 MC15 5 MC0 6 MC1 6 MC2 6 MC3 6 MC15 6 MC0 7 MC1 7 MC2 7 MC3 7 MC15 7 MC0 8 MC1 8 MC2 8 MC3 8 MC15 8 Mail box...

Page 517: ...Undefined R W 0 ID 16 Undefined R W 2 Undefined R W 1 ID 17 Undefined R W 7 ID 28 Undefined R W 6 ID 27 Undefined R W 5 ID 26 Undefined R W 4 ID 25 Undefined R W 3 ID 24 Undefined R W 0 ID 21 Undefine...

Page 518: ...s MCx 2 MCx 3 MCx 4 7 to 0 7 to 0 7 to 0 R W R W R W The initial value of these bits is undefined they must be initialized by writing 0 or 1 7 to 5 ID 20 to ID 18 R W Sets ID 20 to ID 18 in the identi...

Page 519: ...egisters for one mailbox The HCAN has 16 sets of these registers Because message data registers are in RAM their initial values after power on are undefined Be sure to initialize them by writing 0 or...

Page 520: ...6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefi...

Page 521: ...ways read as undefined value and cannot be modified 6 TxSTP 0 R W HTxD Transmission Stop Controls transmission stop of the HTxD pin 0 Enables transmission from the HTxD pin 1 Fixes an output level of...

Page 522: ...tered until message transfer has been completed The reset status bit GSR3 in GSR is set on completion of initialization 13 4 2 Initialization after Hardware Reset After a hardware reset the following...

Page 523: ...ic MCR0 0 GSR3 0 Yes GSR3 0 11 recessive bits received Can bus communication enabled Yes Bit configuration mode Period in which BCR MBCR etc are initialized Settings by user Processing by hardware Ini...

Page 524: ...dle Yes Correction Yes Correction Settings by user Processing by hardware No No No No No BCR setting MBCR setting Mailbox RAM initialization Message transmission method initialization OK IMR setting M...

Page 525: ...ng for the physical delay between networks PHSEG1 is a buffer segment for correcting phase drift positive This segment is extended when synchronization resynchronization is established PHSEG2 is a buf...

Page 526: ...000000 a TSEG1 setting of B 0100 and a TSEG2 setting of B 011 Bit rate 20 2 0 1 3 4 3 1 Mbps Table 13 3 Setting Range for TSEG1 and TSEG2 in BCR TSEG2 BCR14 to BCR12 TSEG1 BCR11 to BCR8 001 010 011 1...

Page 527: ...e transmission methods are available Transmission order determined by message identifier priority Transmission order determined by mailbox number priority Either of the message transmission methods ca...

Page 528: ...tting MBCR setting Mailbox initialization Message transmission method setting Yes No Yes Yes Settings by user Processing by hardware No No Interrupt settings Transmit data setting Arbitration field se...

Page 529: ...The byte length of the data to be transmitted is determined by the data length code in the control field Even if data exceeding the value set in the control field is set in the data field up to the b...

Page 530: ...ted the transmit wait register TXPR is automatically reset and the corresponding bit is set to 1 in the abort acknowledge register ABACK and then an interrupt to the CPU can be requested Also if the c...

Page 531: ...essing by hardware Set TXCR bit corresponding to message to be canceled Message not sent Clear TXCR TXPR ABACK 1 IRR8 1 Clear TXACK Clear ABACK Clear IRR8 Completion of message transmission TXACK 1 Cl...

Page 532: ...BCR setting MBCR setting Mailbox RAM initialization Receive data setting Arbitration field setting Local acceptance filter settings Interrupt settings Message reception Match of identifier in mailbox...

Page 533: ...egister identifier and if a complete match is found the message is stored in the matching mailbox Mailbox 0 has a local acceptance filter mask LAFM that allows Don t Care settings The LAFM setting can...

Page 534: ...LAFM the mailbox comparison sequence does not end at that point but continues from mailbox 1 Therefore the message for mailbox 0 can also be received by another mailbox Note that the same message cann...

Page 535: ...sage the unread message register UMSR is set when a new message is received before the corresponding bit in the receive complete register RXPR has been cleared If the unread interrupt flag IRR9 in the...

Page 536: ...a flowchart of the HCAN sleep mode IRR12 1 Yes MCR5 0 Yes Yes MCR5 0 Clear sleep mode GSR3 1 Yes No No No Yes manual No automatic MCR5 1 Bus idle Initialize TEC and REC Bus operation Settings by user...

Page 537: ...earing by software HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU 2 Clearing by CAN bus operation The cancellation method is selected by bit MCR7 setting in MCR Clearing by CAN bus ope...

Page 538: ...e HCAN halt mode MCR1 1 Yes Settings by user Processing by hardware No Bus idle Set MBCR MCR1 0 CAN bus communication possible Figure 13 14 HCAN Halt Mode Flowchart HCAN halt mode is entered by settin...

Page 539: ...ble 13 4 HCAN Interrupt Sources Name Description Interrupt Flag DMAC Activation ERS0 OVR0 Error passive interrupt TEC 128 or REC 128 IRR5 Not possible Bus off interrupt TEC 256 IRR6 Reset processing i...

Page 540: ...U by a reception interrupt from the HCAN Figure 13 15 shows a DMAC transfer flowchart DMAC initialization Activation source source address destination address transfer count and Yes Yes Settings by us...

Page 541: ...ips PCA82C250 transceiver IC is recommended If any other product is used confirm that it is compatible with the PCA82C250 Figure 13 16 shows a sample connection diagram RS RxD TxD Vref Vcc CANH CANL G...

Page 542: ...re undefined Therefore always initialize mailboxes after a power on reset a transition to software standby mode or a transition to module stop mode After a power on reset recovery from software standb...

Page 543: ...ecessive sequences are counted REC 1 using REC When REC reaches 96 during the count IRR4 and GSR1 are set 13 8 6 Register Access Byte or word access can be performed for all HCAN registers Longword ac...

Page 544: ...itted retains its state To avoid this one of the following countermeasures must be executed Transmission must not be canceled by TXCR When transmission is normally completed after the CAN bus has reco...

Page 545: ...e set at least 50 s after completion of transmission of all messages en bloc transmission Transmission setting should be performed according to the priority Sufficient duration should be taken between...

Page 546: ...Section 13 Controller Area Network HCAN Rev 3 00 Mar 14 2006 Page 508 of 804 REJ09B0104 0300 Downloaded from Elcodis com electronic components distributor...

Page 547: ...synchronous mode Choice of master mode and slave mode Choice of standard mode and bidirectional mode Synchronous serial communication with devices with different clock polarity and clock phase Choice...

Page 548: ...Internal data bus Bus interface SCS SSI Shiftout Shiftin OEI TXI TEI Legend SSCRH SSCRL SSCR2 SSMR SSER SSSR SSTDR0 to SSTDR3 SSRDR0 to SSRDR3 SSTRSR SS control register H SS control register L SS co...

Page 549: ...0 I O Channel 0 SSU chip select input output 1 SSCK1 I O Channel 1 SSU clock input output SSI1 I O Channel 1 SSU data input output SSO1 I O Channel 1 SSU data input output SCS1 I O Channel 1 SSU chip...

Page 550: ...e register_0 SSER_0 SS status register_0 SSSR_0 SS control register 2_0 SSCR2_0 SS transmit data register 0_0 SSTDR0_0 SS transmit data register 1_0 SSTDR1_0 SS transmit data register 2_0 SSTDR2_0 SS...

Page 551: ...ter 1_1 SSRDR1_1 SS receive data register 2_1 SSRDR2_1 SS receive data register 3_1 SSRDR3_1 SS shift register_1 SSTRSR_1 3 Channel 2 SS control register H_2 SSCRH_2 SS control register L_2 SSCRL_2 SS...

Page 552: ...er mode is selected transfer clocks are output from the SSCK pin When the CE bit in SSSR is set this bit is automatically cleared 0 Slave mode is selected 1 Master mode is selected 6 BIDE 0 R W Bidire...

Page 553: ...after clearing the SOLP bit to 0 using the MOV instruction 0 Output level can be changed by the SOL bit 1 Output level cannot be changed by the SOL bit This bit is always read as 1 2 SCKS 0 R W SSCK P...

Page 554: ...d clock synchronous mode 0 SSU mode 1 Clock synchronous mode 5 SRES 0 R W Software Reset Setting this bit to 1 forcibly resets the SSU internal sequencer After that this bit is automatically cleared T...

Page 555: ...first 1 MSB first 6 CPOS 0 R W Clock Polarity Select Selects the SSCK clock polarity 0 High output in idle mode and low output in active mode 1 Low output in idle mode and high output in active mode...

Page 556: ...s enabled 6 RE 0 R W Receive Enable When this bit is set to 1 reception is enabled 5 4 All 0 R W Reserved These bits are always read as 0 The write value should always be 0 3 TEIE 0 R W Transmit End I...

Page 557: ...overrun error occurs indicating abnormal termination SSRDR stores 1 frame receive data before an overrun error occurs and loses data to be received later While ORER 1 consecutive serial reception cann...

Page 558: ...ether or not SSTDR contains transmit data Setting conditions When the TE bit in SSER is 0 When data is transferred from SSTDR to SSTRSR and SSTDR is ready to be written to Clearing conditions When wri...

Page 559: ...suming transfer after incomplete error Setting condition When a low level is input to the SCS pin in master mode the MSS bit in SSCRH is set to 1 When the SCS pin is changed to 1 during transfer in sl...

Page 560: ...rain Select Selects whether the SCS pin is used as a CMOS or an NMOS open drain output 0 CMOS output 1 NMOS open drain output 4 TENDSTS 0 R W Selects the timing of setting the TEND bit valid in SSU an...

Page 561: ...the transmit data written in SSTDR to SSTRSR and starts serial transmission If the next transmit data has already been written to SSTDR during serial transmission the SSU performs consecutive serial...

Page 562: ...ed by bits DATS1 and DATS0 in SSCRL SSRDR0 is valid When 16 bit data length is selected SSRDR0 and SSRDR1 are valid When 32 bit data length is selected SSRDR0 to SSRDR3 are valid Be sure not to access...

Page 563: ...Valid Invalid 2 Invalid Invalid Valid Invalid 3 Invalid Invalid Valid Invalid 14 3 9 SS Shift Register SSTRSR SSTRSR is a shift register that transmits and receives serial data When data is transferre...

Page 564: ...used as an input pin 14 4 2 Relationship of Clock Phase Polarity and Data The relationship of clock phase polarity and transfer data depends on the combination of the CPOS and CPHS bits in SSMR Figure...

Page 565: ...res 14 3 3 and 4 However even if both the TE and RE bits are set to 1 transmission and reception are not performed simultaneously Either the TE or RE bit must be selected The SSU transmits serial data...

Page 566: ...and input output pin functions are shown in tables 14 2 to 14 4 Table 14 4 Communication Modes and Pin States of SSI and SSO Pins Register Setting Pin State Communication Mode SSUMS BIDE MSS TE RE SS...

Page 567: ...Clock synchronous communication mode 1 Input 1 0 1 Output Legend Not used as SSU pin can be used as I O port Table 14 6 Communication Modes and Pin States of SCS Pin Register Setting Pin State Communi...

Page 568: ...es of the RDRF and ORER bits and SSRDR Those bits retain the previous values Start setting initial values 1 2 3 4 End Set a bit in ICR to 1 Clear SSUMS in SSCRH to 0 and specify bits DATS1 and DATS0 S...

Page 569: ...it in SSSR to 0 and the SSTDR contents are transferred to SSTRSR After that the SSU sets the TDRE bit to 1 and starts transmission At this time if the TIE bit in SSER is set to 1 a TXI interrupt is ge...

Page 570: ...Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 SSO TDRE TEND LSI operation User operation LSI operation User operation LSI operation User operation TXI...

Page 571: ...DR The TDRE bit is automatically cleared to 0 by writing data to SSTDR 4 Procedure for data transmission end To end data transmission confirm that the TEND bit is cleared to 0 After completion of tran...

Page 572: ...is input to the SSCK pin the SSU receives data in synchronization with the transfer clock When 1 frame data has been received the RDRF bit in SSSR is set to 1 and the receive data is stored in SSRDR A...

Page 573: ...t 7 Bit 7 LSI operation Dummy read SSRDR0 Dummy readSSRDR0 Read SSRDR0 User operation LSI operation User operation LSI operation User operation SSTDR0 LSB first transmission SSTDR0 MSB first transmiss...

Page 574: ...g the RE bit reception is resumed No Yes Yes No Start Initial setting Dummy read SSRDR Read SSSR RDRF 1 ORER 1 Consecutive data reception Read received data in SSRDR RDRF automatically cleared RE 0 Re...

Page 575: ...reception is not resumed 5 Procedure for consecutive data transmission reception To continue serial data transmission reception confirm that the TDRE bit is 1 meaning that SSTDR is ready to be writte...

Page 576: ...r occurs At this time the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0 Note While the CE bit is set to 1 transmission or reception is not resumed Clear the CE bit to 0 before resuming th...

Page 577: ...bit to 0 does not change the values of the RDRF and ORER bits and SSRDR Those bits retain the previous values Start setting initial values 1 2 3 4 End Set a bit in ICR to 1 Set SSUMS in SSCRL to 1 an...

Page 578: ...1 and starts transmission At this time if the TIE bit in SSER is set to 1 a TXI interrupt is generated When 1 frame data has been transferred with TDRE 0 the SSTDR contents are transferred to SSTRSR...

Page 579: ...is automatically cleared to 0 by writing data to SSTDR 4 Procedure for data transmission end To end data transmission confirm that the TEND bit is cleared to 0 After completion of transmitting the las...

Page 580: ...is stored in SSRDR At this time if the RIE bit is set to 1 an RXI interrupt is generated The RDRF bit is automatically cleared to 0 by reading SSRDR When the RDRF bit has been set to 1 at the 8th risi...

Page 581: ...matically cleared RE 0 Read receive data in SSRDR End reception Overrun error processing Clear ORER in SSSR End reception Note Hatching boxes represent SSU internal operations No Figure 14 16 Flowchar...

Page 582: ...sumed 5 Procedure for consecutive data transmission reception To continue serial data transmission reception confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to After that data...

Page 583: ...condition shown in table 14 7 is satisfied an interrupt is requested Clear the interrupt source by CPU or DMAC data transfer Table 14 7 Interrupt Sources Channel Abbreviation Interrupt Source Symbol I...

Page 584: ...earing module stop mode attention is required to the following When using the SSU channel 1 or 2 module stop mode of the SSU channel 1 or 2 is not cleared without clearing both 1 and 2 bits listed bel...

Page 585: ...r unit 1 Conversion time 7 4 s per channel at 35 MHz operation Two kinds of operating modes Single mode Single channel A D conversion Scan mode Continuous A D conversion on 1 to 4 channels or 1 to 8 c...

Page 586: ...ster Multiplexer Legend ADCR_0 A D control register_0 ADCSR_0 A D control status register_0 ADDRA_0 A D data register A_0 ADDRB_0 A D data register B_0 ADDRC_0 A D data register C_0 ADDRD_0 A D data r...

Page 587: ...egister Multiplexer Legend ADCR_1 A D control register_1 ADCSR_1 A D control status register_1 ADDRA_1 A D data register A_1 ADDRB_1 A D data register B_1 ADDRC_1 A D data register C_1 ADDRD_1 A D dat...

Page 588: ...trigger input pin 0 ADTRG0 Input External trigger input for starting A D conversion Analog power supply pin 0 AVCC 0 Input Analog block power supply 1 AD_1 Analog input pin 8 AN8 Input Analog inputs...

Page 589: ...register D_0 ADDRD_0 A D data register E_0 ADDRE_0 A D data register F_0 ADDRF_0 A D data register G_0 ADDRG_0 A D data register H_0 ADDRH_0 A D control status register_0 ADCSR_0 A D control register...

Page 590: ...ad as 0 The data bus between the CPU and the A D converter has a 16 bit width The data can be read directly from the CPU ADDR must not be accessed in 8 bit units and must be accessed in 16 bit units 1...

Page 591: ...r reading ADF 1 When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled be sure to read the flag after writing 0 to it When the DMAC is activated by an ADI in...

Page 592: ...0101 AN5 0110 AN6 0111 AN7 1XXX Setting prohibited When SCANE 1 and SCANS 0 0000 AN0 0001 AN0 and AN1 0010 AN0 to AN2 0011 AN0 to AN3 0100 AN4 0101 AN4 and AN5 0110 AN4 to AN6 0111 AN4 to AN7 1XXX Set...

Page 593: ...om TPU is enabled 10 Setting prohibited 11 A D conversion start by the ADTRG pin is enabled 5 4 SCANE SCANS 0 0 R W R W Scan Mode These bits select the A D conversion operating mode 0X Single mode 10...

Page 594: ...put of the specified single channel 1 A D conversion for the selected channel is started when the ADST bit in ADCSR is set to 1 by software or an external trigger input 2 When A D conversion is comple...

Page 595: ...the ADST bit in ADCSR is set to 1 by software TPU or an external trigger input A D conversion starts on the first channel in the group Consecutive A D conversion on a maximum of four channels SCANE an...

Page 596: ...2 AN2 operation state Channel 3 AN3 operation state Waiting for conversion A D conver sion 1 A D conversion result 3 Waiting for conversion Waiting for conversion Waiting for conversion A D conversio...

Page 597: ...D varies depending on the timing of the write access to ADCSR The total conversion time therefore varies within the ranges indicated in table 15 3 In scan mode the values given in table 15 3 apply to...

Page 598: ...an Mode CKS1 CKS0 Conversion Time Number of States 0 512 Fixed 0 1 256 Fixed 0 128 Fixed 1 1 64 Fixed 15 4 4 External Trigger Input Timing A D conversion can be externally triggered When the TRGS1 and...

Page 599: ...n The number of A D converter digital output codes Quantization error The deviation inherent in the A D converter given by 1 2 LSB see figure 15 7 Offset error The deviation of the analog input voltag...

Page 600: ...ut Ideal A D conversion characteristic Analog input voltage Figure 15 7 A D Conversion Accuracy Definitions FS Digital output Ideal A D conversion characteristic Nonlinearity error Analog input voltag...

Page 601: ...hin the sampling time if the sensor output impedance exceeds 5 k charging may be insufficient and it may not be possible to guarantee the A D conversion accuracy However if a large capacitance is prov...

Page 602: ...s VAN AVcc1 Relation between AVcc0 AVcc1 AVss and Vcc Vss As the relationship between AVcc0 AVcc1 AVss and Vcc Vss set AVcc0 Vcc 0 3 V AVcc1 Vcc 0 3 V and AVss Vss If the A D converter is not used set...

Page 603: ...d and so an error may arise Also when A D conversion is performed frequently as in scan mode if the current charged and discharged by the capacitance of the sample and hold circuit in the A D converte...

Page 604: ...Hold Function in Software Standby Mode When this LSI enters software standby mode with A D conversion enabled the A D conversion are retained and the analog current is equal to as during A D conversi...

Page 605: ...the CPU to all byte data word data and longword data The on chip RAM can be enabled or disabled by means of the RAME bit in the system control register SYSCR For details on SYSCR refer to section 3 2...

Page 606: ...Section 16 RAM Rev 3 00 Mar 14 2006 Page 568 of 804 REJ09B0104 0300 Downloaded from Elcodis com electronic components distributor...

Page 607: ...d of on chip program This LSI has a programming erasing program After downloading this program to the on chip RAM programming erasing can be performed by setting the parameters Programming erasing tim...

Page 608: ...FCCS FPCS FECS FKEY FMATS FTDAR RAMER Control unit Memory MAT unit Flash memory User MAT 256 kbytes User boot MAT 10 kbytes Operating mode Module bus Mode pins Internal data bus 32 bits Internal addre...

Page 609: ...mer mode are shown in table 17 1 Reset state Programmer mode User mode User program mode User boot mode Boot mode On board programming mode RES 0 R E S 0 User mode setting U s e r b o o t m o d e s e...

Page 610: ...a SCI From desired device via RAM From desired device via RAM Via programmer RAM emulation O O Reset initiation MAT Embedded program storage area User MAT User boot MAT 2 Transition to user mode Chang...

Page 611: ...ATs the memory MATs must be switched by the flash MAT select register FMATS The user MAT or user boot MAT can be read in all modes However the user boot MAT can be programmed or erased only in boot mo...

Page 612: ...003FFF H 01FFFF H 00607F H 006FFF H 00707F H 007FFF H 00807F H 00FFFF H 01007F Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes Programming u...

Page 613: ...rogram for user program mode and user boot mode is made by the user Figure 17 5 shows the procedure for creating the procedure program For details see section 17 8 2 User Program Mode Download on chip...

Page 614: ...nts can be changed after completion of download 3 Initialization of Programming Erasing A pulse with the specified period must be applied when programming or erasing The specified pulse width is made...

Page 615: ...downloaded on chip program is left in the on chip RAM even after programming erasing completes download and initialization are not required when the same processing is executed consecutively 17 6 Inpu...

Page 616: ...register FMATS Flash transfer destination address register FTDAR Programming Erasing Interface Parameters Download pass and fail result parameter DPFR Flash pass and fail result parameter FPFR Flash p...

Page 617: ...ogramming or erasing the user MAT in user boot mode 2 The setting may be required according to the combination of initiation mode and read target memory MAT 17 7 1 Programming Erasing Interface Regist...

Page 618: ...e reset input period period of RES 0 of at least 100 s 0 Flash memory operates normally Error protection is invalid Clearing condition At a power on reset 1 An error occurs during programming erasing...

Page 619: ...terrupts must be disabled during download This bit is cleared to 0 when download is completed During program download initiated with this bit particular processing which accompanies bank switching of...

Page 620: ...nloaded 0 Programming program is not selected Clearing condition When transfer is completed 1 Programming program is selected 3 Flash Erase Code Select Register FECS FECS selects the erasing program t...

Page 621: ...is written to FKEY writing to the SCO bit in FCCS is enabled When a value other than H A5 is written the SCO bit cannot be set to 1 Therefore the on chip program cannot be downloaded to the on chip R...

Page 622: ...ect The memory MATs can be switched by writing a value to FMATS When H AA is written to FMATS the user boot MAT is selected When a value other than H AA is written the user MAT is selected Switch the...

Page 623: ...s executed by setting the SCO bit in FCCS to 1 Make sure that this bit is cleared to 0 before setting the SCO bit to 1 and the value of FTDAR to should be within the range of H 00 to H 02 0 The value...

Page 624: ...arameters are used in download control initialization before programming or erasing programming and erasing Table 17 4 shows the usable parameters and target modes The meaning of the bits in the flash...

Page 625: ...8 byte program data is prepared by filling the dummy code H FF The boundary of the start address of the programming destination on the user MAT is aligned at an address where the lower eight bits A7 t...

Page 626: ...When the program to be downloaded is not selected more than two types of programs are selected or a program which is not mapped is selected an error occurs 0 Download program selection is normal 1 Dow...

Page 627: ...the initialization result 7 6 5 4 3 0 SF 2 1 FQ Bit Bit Name Bit Bit Name Initial Value R W Description 7 to 2 Unused These bits return 0 1 FQ R W Frequency Error Detect Compares the specified CPU op...

Page 628: ...5 EE R W Programming Execution Error Detect Writes 1 to this bit when the specified data could not be written because the user MAT was not erased If this bit is set to 1 there is a high possibility t...

Page 629: ...for the program data is abnormal 1 WA R W Write Address Error Detect When the following items are specified as the start address of the programming destination an error occurs An area other than flas...

Page 630: ...3 Error Protection 0 Normal operation FLER 0 1 Error protection state and programming cannot be performed FLER 1 5 EE R W Erasure Execution Error Detect Returns 1 when the user MAT could not be erased...

Page 631: ...g is abnormal value other than H 5A 3 EB R W Erase Block Select Error Detect Checks whether the specified erase block number is in the block range of the user MAT and returns the result 0 Setting of e...

Page 632: ...0 15 to 0 F15 to F0 R W Frequency Set These bits set the operating frequency of the CPU When the PLL multiplication function is used set the multiplied frequency The setting value must be calculated a...

Page 633: ...24 MOA24 26 MOA26 25 MOA25 23 MOA23 22 MOA22 21 MOA21 20 MOA20 19 MOA19 16 MOA16 18 MOA18 17 MOA17 15 MOA15 14 MOA14 13 MOA13 12 MOA12 11 MOA11 8 MOA8 10 MOA10 9 MOA9 7 MOA7 6 MOA6 5 MOA5 4 MOA4 3 MOA...

Page 634: ...MOD30 29 MOD29 28 MOD28 27 MOD27 24 MOD24 26 MOD26 25 MOD25 23 MOD23 22 MOD22 21 MOD21 20 MOD20 19 MOD19 16 MOD16 18 MOD18 17 MOD17 15 MOD15 14 MOD14 13 MOD13 12 MOD12 11 MOD11 8 MOD8 10 MOD10 9 MOD9...

Page 635: ...block EB0 and a value of 11 corresponds to block EB11 An error occurs when a value outside the range from 0 to 11 is set 31 R W 30 R W 29 R W 28 R W 27 R W 24 R W 26 R W 25 R W Bit Bit Name Initial V...

Page 636: ...Bit Name Initial Value R W Description 7 to 4 0 R Reserved These are read only bits and cannot be modified 3 RAMS 0 R W RAM Select Selects the function which emulates the flash memory using the on ch...

Page 637: ...0 1 Boot mode 1 0 User program mode 1 1 17 8 1 Boot Mode Boot mode executes programming erasing of the user MAT or user boot MAT by means of the control command and program data transmitted from the...

Page 638: ...t end sign When the host receives this bit adjustment end sign normally it transmits 1 byte of H 55 to this LSI When reception is not executed normally initiate boot mode again The bit rate may not be...

Page 639: ...n H 00 transmission adjustment completed Bit rate adjustment Processing of inquiry setting command All user MAT and user boot MAT erasure Wait for program data Wait for erase block data Read check com...

Page 640: ...ed the state of waiting for erase block data is entered The erase block number must be transmitted after the erasing command is transmitted When the erasure is finished the erase block number must be...

Page 641: ...flash memory If a reset is input the reset must be released after the reset input period period of RES 0 of at least 100 s When programming program data is prepared Programming erasing procedure progr...

Page 642: ...ure program do not overlap Figure 17 10 shows the area of the on chip program to be downloaded H FFBFFF Programming erasing program entry System use area 15 bytes DPFR Return value 1 byte FTDAR settin...

Page 643: ...ogramming is completed No Set FKEY to H 5A Clear FKEY to 0 1 2 4 5 6 7 8 9 10 11 12 13 14 15 1 3 Download Initialization Programming Initialization JSR FTDAR setting 32 Initialization error processing...

Page 644: ...bit is executed in the on chip RAM When the SCO bit is set to 1 download is started automatically Since the SCO bit is cleared to 0 when the procedure program is resumed the SCO bit cannot be confirme...

Page 645: ...arameter is different from that before downloading check the SS bit or FK bit in the DPFR parameter to confirm the download program selection and FKEY setting respectively 6 The operating frequency of...

Page 646: ...ll programming completes When the bus mastership is moved to other than the CPU such as to the DMAC the error protection state is entered Therefore make sure the DMAC does not acquire the bus 10 FKEY...

Page 647: ...ximum must be allocated in RAM 13 The return value in the programming program the FPFR parameter is determined 14 Determine whether programming of the necessary data has finished If more than 128 byte...

Page 648: ...gram FPFR 0 No Initialization error processing Disable interrupts and bus master operation other than CPU Clear FKEY to 0 Set FEBS parameter Yes FPFR 0 No Clear FKEY and erasing error processing Yes R...

Page 649: ...er Program Mode 2 Set the FEBS parameter necessary for erasure Set the erase block number FEBS parameter of the user MAT in general register ER0 If a value other than an erase block number of the user...

Page 650: ...Erasing Programming Start procedure program Initialize erasing program Set FTDAR to H 02 specify download destination H FFB000 Download programming program Initialize programming program End procedur...

Page 651: ...3 User Boot Mode Branching to a programming erasing program prepared by the user enables user boot mode which is a user arbitrary boot mode to be used Only the user MAT can be programmed erased in use...

Page 652: ...error processing Set FMATS to H AA to select user boot MAT User boot MAT selection state User MAT selection state User boot MAT selection state Note The MAT must be switched by FMATS to perform the pr...

Page 653: ...rs from which memory MAT the interrupt vector is read is undetermined Perform memory MAT switching in accordance with the description in section 17 11 Switching between User MAT and User Boot MAT Exce...

Page 654: ...error processing Disable interrupts and bus master operation other than CPU Clear FKEY to 0 Set FEBS parameter Yes No Clear FKEY and erasing error processing Yes Required block erasing is completed N...

Page 655: ...this on chip RAM area is not available for use Since the on chip program uses a stack area allocate 128 bytes at the maximum as a stack area Download requested by setting the SCO bit in FCCS to 1 sho...

Page 656: ...even when the data stored is normal program data Therefore the data should be transferred to the on chip RAM to place the address that the FMPDR parameter indicates in an area other than the flash mem...

Page 657: ...O O Decision of download result O O O Operation for download error O O O Operation for setting initialization parameter O O O Execution of initialization O O Decision of initialization result O O O Op...

Page 658: ...ad O O Operation for clearing FKEY O O O Decision of download result O O O Operation for download error O O O Operation for setting initialization parameter O O O Execution of initialization O O Decis...

Page 659: ...peration for setting initialization parameter O O O Execution of initialization O O Decision of initialization result O O O Operation for initialization error O O O NMI handling routine O O Operation...

Page 660: ...Operation for download error O O O Operation for setting initialization parameter O O O Execution of initialization O O Decision of initialization result O O O Operation for initialization error O O...

Page 661: ...s indicated by the FPFR parameter Table 17 12 Hardware Protection Function to be Protected Item Description Download Programming Erasing Reset protection The programming erasing interface registers ar...

Page 662: ...tered when the RAMS bit in the RAM emulation register RAMER is set to 1 O O 17 9 3 Error Protection Error protection is a mechanism for aborting programming or erasure when a CPU runaway occurs or ope...

Page 663: ...tion diagram in figure 17 16 shows transitions to and from the error protection state Reset hardware protection Programming erasing mode Error protection mode Error protection mode software standby Re...

Page 664: ...area specified by RAMER and the overlaid RAM area The emulation can be performed in user mode and user program mode Figure 17 17 shows an example of emulating realtime programming of the user MAT Not...

Page 665: ...R from among the eight blocks EB0 to EB7 of the user MAT To overlay a part of the on chip RAM with block EB0 for realtime emulation set the RAMS bit in RAMER to 1 and bits RAM2 to RAM0 to B 000 For pr...

Page 666: ...MER to 0 to cancel the overlaid RAM 2 Transfer the user created procedure program to the on chip RAM 3 Start the procedure program and download the on chip program to the on chip RAM The start address...

Page 667: ...ng memory MAT switching 4 After the memory MATs have been switched take care because the interrupt vector table will also have been switched If interrupt processing is to be the same before and after...

Page 668: ...program adjusts the bit rate to achieve serial communication with the host Initiating boot mode enables starting of the boot program and entry to the bit rate adjustment state The program receives the...

Page 669: ...erasing wait Checking Inquiry Response Erasing Programming Reset Bit rate adjustment state Operations for erasing user MATs and user boot MATs Operations for inquiry and selection Operations for prog...

Page 670: ...adjustment of the bit rate the protocol for serial communications between the host and the boot program is as shown below 1 One byte commands and one byte responses These one byte commands and one by...

Page 671: ...inquiries selection programming erasing and checking Response one byte Response to an inquiry Size one byte The amount of data for transmission excluding the command amount of data and checksum Checks...

Page 672: ...iplied clock types the number of multiplication ratios and the values of each multiple H 23 Operating clock frequency inquiry Inquiry regarding the maximum and minimum values of the main clock and per...

Page 673: ...e in response to the supported device inquiry Command H 20 Command H 20 one byte Inquiry regarding supported devices Response H 30 Size Number of devices Number of characters Device code Product name...

Page 674: ...matches Error response H 90 ERROR Error response H 90 one byte Error response to the device selection command ERROR one byte Error code H 11 Sum check error H 21 Device code error that is the device...

Page 675: ...resents the modes Mode one byte A clock mode returned in reply to the supported clock mode inquiry SUM one byte Checksum Response H 06 Response H 06 one byte Response to the clock mode selection comma...

Page 676: ...iplied clock types which are the main and peripheral clocks the number of types will be H 02 Number of multiplication ratios one byte The number of multiplication ratios for each type e g the number o...

Page 677: ...requencies Number of operating clock frequencies one byte The number of supported operating clock frequency types e g when there are two operating clock frequency types which are the main and peripher...

Page 678: ...start address four byte Start address of the area Area last address four byte Last address of the area There are as many groups of data representing the start and last addresses as there are areas SUM...

Page 679: ...er of blocks block start addresses and block last addresses Number of blocks one byte The number of erased blocks Block start address four bytes Start address of a block Block last Address four bytes...

Page 680: ...one byte The number of multiplication ratios to which the device can be set Multiplication ratio 1 one byte The value of multiplication or division ratios for the main operating frequency Multiplicati...

Page 681: ...hen the value is out of this range an input frequency error is generated 2 Multiplication ratio The received value of the multiplication ratio or division ratio is checked to ensure that it matches th...

Page 682: ...bit rate is selectable the rate will be set in the register after sending ACK in response The host will send an ACK with the new bit rate for confirmation and the boot program will response with that...

Page 683: ...byte Transition to programming erasing state Response H 06 Response H 06 one byte Response to transition to programming erasing state The boot program will send ACK when the user MAT and user boot MA...

Page 684: ...required information should be made such as the multiplication ratio inquiry H 22 or operating frequency inquiry H 23 which are needed for a new bit rate selection 6 A new bit rate should be selected...

Page 685: ...on Transfers the user boot MAT programming program H 43 User MAT programming selection Transfers the user MAT programming program H 50 128 byte programming Programs 128 bytes of data H 48 Erasing sele...

Page 686: ...ng to the method specified by the selection command When more than 128 byte data is programmed 128 byte commands should repeatedly be executed Sending a 128 byte programming command with H FFFFFFFF as...

Page 687: ...blocks are to be erased Sending a block erasure command from the host with the block number H FF will stop the erasure operating On completion of erasing the boot program will wait for selection of p...

Page 688: ...tion ERROR 1 byte Error code H 54 Selection processing error transfer error occurs and processing is not completed b User MAT Programming Selection The boot program will transfer a program for user MA...

Page 689: ...yte programming On completion of programming the boot program will return ACK Error Response H D0 ERROR Error response H D0 one byte Error response for 128 byte programming ERROR one byte Error code H...

Page 690: ...1 Checksum error H 53 Programming error An error has occurred in programming and programming cannot be continued d Erasure Selection The boot program will transfer the erasure program User MAT data is...

Page 691: ...D8 one byte Response to Erasure ERROR one byte Error code H 11 Sum check error H 29 Block number error Block number is incorrect H 51 Erasure error An error has occurred during erasure On receiving b...

Page 692: ...area setting is incorrect Read address 4 bytes Start address to be read from Read size 4 bytes Size of data to be read SUM 1 byte Checksum Response H 52 Read size Data SUM Response H 52 1 byte Respons...

Page 693: ...UM one byte Sum check for data being transmitted h User Program Sum Check The boot program will return the byte by byte total of the contents of the bytes of the user program Command H 4B Command H 4B...

Page 694: ...ll user MATs are blank H FF the boot program will return ACK Error Response H CD H 52 Error Response H CD one byte Error response to the blank check of user MATs Error code H 52 one byte Erasure has n...

Page 695: ...H 5F Erase block specification wait erasure is completed Table 17 18 Error Code Code Description H 00 No error H 11 Sum check error H 12 Program size error H 21 Device code mismatch error H 22 Clock m...

Page 696: ...diately after programming erasing has finished secure the reset input period period of RES 0 of at least 100 s Transition to the reset state during programming erasing is inhibited If a reset is input...

Page 697: ...eeded measures should be taken by user A periodic interrupt generated by the WDT can be used as the measures as an example The interrupt generation cycle should take into consideration time to downloa...

Page 698: ...Section 17 Flash Memory 0 18 m F ZTAT Version Rev 3 00 Mar 14 2006 Page 660 of 804 REJ09B0104 0300 Downloaded from Elcodis com electronic components distributor...

Page 699: ...supports three types of clocks a system clock provided to the CPU and bus masters a peripheral module clock provided to the peripheral modules and an external clock provided to the external bus These...

Page 700: ...nitial Value R W 15 PSTOP1 0 R W 14 0 R W 13 POSEL1 0 R W 12 0 R W 11 0 R W 10 ICK2 0 R W 9 ICK1 1 R W 8 ICK0 0 R W Bit Bit Name Initial Value R W 7 0 R W 6 PCK2 0 R W 5 PCK1 1 R W 4 PCK0 0 R W 3 0 R...

Page 701: ...ICK0 0 1 0 R W R W R W System Clock I Select These bits select the frequency of the system clock provided to the CPU and DMAC The ratio to the input clock is as follows 000 8 001 4 010 2 011 1 1XX Set...

Page 702: ...module clock higher than that of the system clock the clocks will have the same frequency in reality 3 0 R W Reserved This bit is always read as 0 The write value should always be 0 2 1 0 BCK2 BCK1 B...

Page 703: ...used When the clock is provided by connecting a crystal resonator a crystal resonator having a frequency of 4 to 9 MHz should be connected EXTAL XTAL Rd CL2 CL1 10 pF CL1 CL2 22 pF Figure 18 2 Connect...

Page 704: ...en a XTAL pin left open EXTAL XTAL External clock input b Counter clock input on XTAL pin Figure 18 4 External Clock Input Examples For the input conditions of the external clock refer to table 21 4 C...

Page 705: ...processing of modules such as a timer and SCI differs before and after changing the clock division ratio In addition wait time for clearing software standby mode differs by changing the clock divisio...

Page 706: ...voltage exceeding the maximum rating is not applied to the resonator pin 18 5 3 Notes on Board Design When using the crystal resonator place the crystal resonator and its load capacitors as close as...

Page 707: ...ere 2 CB is a laminated ceramic capacitor This LSI CB 2 VCL 41 VSS 39 VCC 22 VSS 20 CB 2 C1 1 Figure 18 7 Connection Example of Bypass Capacitor 18 5 4 Notes on Input Clock Frequency The frequency of...

Page 708: ...Section 18 Clock Pulse Generator Rev 3 00 Mar 14 2006 Page 670 of 804 REJ09B0104 0300 Downloaded from Elcodis com electronic components distributor...

Page 709: ...ree power down modes Sleep mode All module clock stop mode Software standby mode Table 19 1 shows conditions for making a transition to a power down mode states of the CPU and peripheral modules and c...

Page 710: ...interrupt 2 Interrupt 1 SSBY 0 SSBY 0 ACSE 1 MSTPCR H F 0 F FFFFFF SSBY 1 RES pin high Transition after exception handling Reset state Program execution state Program halted state Sleep mode Notes 1 N...

Page 711: ...Shifts to sleep mode after the SLEEP instruction is executed 1 Shifts to software standby mode after the SLEEP instruction is executed This bit does not change when clearing the software standby mode...

Page 712: ...settling time is necessary Refer to table 19 2 to set the standby time While oscillation is being settled the timer is counted on the P clock frequency Careful consideration is required in multi clock...

Page 713: ...MSTPCRA Bit Bit Name Initial Value R W 15 ACSE 0 R W 14 MSTPA14 0 R W 13 MSTPA13 0 R W 12 MSTPA12 0 R W 11 MSTPA11 1 R W 10 MSTPA10 1 R W 9 MSTPA9 1 R W 8 MSTPA8 1 R W Bit Bit Name Initial Value R W...

Page 714: ...its are always read as 0 The write value should always be 0 13 MSTPA13 0 R W DMA controller DMAC 12 MSTPA12 0 R W Reserved These bits are always read as 0 The write value should always be 0 11 10 9 8...

Page 715: ...ould always be 1 12 MSTPB12 1 R W Serial communication interface_4 SCI_4 11 MSTPB11 1 R W Serial communication interface_3 SCI_3 10 9 8 7 6 5 4 3 2 1 0 MSTPB10 MSTPB9 MSTPB MSTPB7 MSTPB6 MSTPB5 MSTPB4...

Page 716: ...R W 0 MSTPC0 0 R W Bit Bit Name Initial Value R W Module 15 14 13 12 MSTPC15 MSTPC14 MSTPC13 MSTPC12 1 1 1 1 R W R W R W R W Reserved These bits are always read as 1 The write value should always be 1...

Page 717: ...eared If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0 this LSI enters sleep mode When sleep mode is cleared by an interrupt multi clock mode is restored If a SLEEP instr...

Page 718: ...ter the stipulated reset input duration driving the RES pin high makes the CPU start the reset exception processing 3 Clearing by reset caused by watchdog timer overflow Sleep mode is exited by an int...

Page 719: ...RES pin 1 Clearing by interrupt When an NMI or IRQ0 to IRQ14 interrupt request signal is input clock oscillation starts and after the elapse of the time set in bits STS4 to STS0 in SBYCR stable clocks...

Page 720: ...to set the standby time Table 19 2 Oscillation Settling Time Settings P MHz STS4 STS3 STS2 STS1 STS0 Standby Time 35 25 20 Unit 0 0 0 0 0 Reserved s 1 Reserved 1 0 Reserved 1 Reserved 1 0 0 Reserved...

Page 721: ...0 1 0 0 0 2048 157 5 204 8 256 0 1 4096 0 32 0 41 0 51 ms 1 0 16384 1 26 1 64 2 05 1 32765 2 52 3 28 4 10 1 0 0 65536 5 04 6 55 8 19 1 131072 10 08 13 11 16 38 1 0 262144 20 16 26 21 32 77 1 524288 40...

Page 722: ...it in INTCR cleared to 0 falling edge specification then the NMIEG bit is set to 1 rising edge specification the SSBY bit is set to 1 and a SLEEP instruction is executed causing a transition to softwa...

Page 723: ...bled and the pin becomes an input port Disabling B output can reduce electromagnetic interference EMI Take it into consideration for design of the user system board Tables 19 3 shows the states of the...

Page 724: ...bit MSTPA13 may not be set to 1 Setting of the DMAC module stop mode should be carried out only when the DMAC is not activated For details refer to section 7 DMA Controller DMAC 19 9 4 On Chip Periph...

Page 725: ...gister bits Bit configurations of the registers are listed in the same order as the register addresses Reserved bits are indicated by in the bit name column Space in the bit name field indicates that...

Page 726: ...PR 16 H FEA10 HCAN 16 4P 4P Interrupt register IRR 16 H FEA12 HCAN 16 4P 4P Mailbox interrupt mask register MBIMR 16 H FEA14 HCAN 16 4P 4P Interrupt mask register IMR 16 H FEA16 HCAN 16 4P 4P Receive...

Page 727: ...4P Message control 2 4 MC2 4 8 H FEA33 HCAN 16 4P 4P Message control 2 5 MC2 5 8 H FEA34 HCAN 16 4P 4P Message control 2 6 MC2 6 8 H FEA35 HCAN 16 4P 4P Message control 2 7 MC2 7 8 H FEA36 HCAN 16 4P...

Page 728: ...4P Message control 5 8 MC5 8 8 H FEA4F HCAN 16 4P 4P Message control 6 1 MC6 1 8 H FEA50 HCAN 16 4P 4P Message control 6 2 MC6 2 8 H FEA51 HCAN 16 4P 4P Message control 6 3 MC6 3 8 H FEA52 HCAN 16 4P...

Page 729: ...ontrol 9 4 MC9 4 8 H FEA6B HCAN 16 4P 4P Message control 9 5 MC9 5 8 H FEA6C HCAN 16 4P 4P Message control 9 6 MC9 6 8 H FEA6D HCAN 16 4P 4P Message control 9 7 MC9 7 8 H FEA6E HCAN 16 4P 4P Message c...

Page 730: ...sage control 12 8 MC12 8 8 H FEA87 HCAN 16 4P 4P Message control 13 1 MC13 1 8 H FEA88 HCAN 16 4P 4P Message control 13 2 MC13 2 8 H FEA89 HCAN 16 4P 4P Message control 13 3 MC13 3 8 H FEA8A HCAN 16 4...

Page 731: ...3 MD0 3 8 H FEAB2 HCAN 16 4P 4P Message data 0 4 MD0 4 8 H FEAB3 HCAN 16 4P 4P Message data 0 5 MD0 5 8 H FEAB4 HCAN 16 4P 4P Message data 0 6 MD0 6 8 H FEAB5 HCAN 16 4P 4P Message data 0 7 MD0 7 8 H...

Page 732: ...AN 16 4P 4P Message data 3 8 MD3 8 8 H FEACF HCAN 16 4P 4P Message data 4 1 MD4 1 8 H FEAD0 HCAN 16 4P 4P Message data 4 2 MD4 2 8 H FEAD1 HCAN 16 4P 4P Message data 4 3 MD4 3 8 H FEAD2 HCAN 16 4P 4P...

Page 733: ...AN 16 4P 4P Message data 7 4 MD7 4 8 H FEAEB HCAN 16 4P 4P Message data 7 5 MD7 5 8 H FEAEC HCAN 16 4P 4P Message data 7 6 MD7 6 8 H FEAED HCAN 16 4P 4P Message data 7 7 MD7 7 8 H FEAEE HCAN 16 4P 4P...

Page 734: ...P Message data 10 8 MD10 8 8 H FEB07 HCAN 16 4P 4P Message data 11 1 MD11 1 8 H FEB08 HCAN 16 4P 4P Message data 11 2 MD11 2 8 H FEB09 HCAN 16 4P 4P Message data 11 3 MD11 3 8 H FEB0A HCAN 16 4P 4P Me...

Page 735: ...4 2 8 H FEB21 HCAN 16 4P 4P Message data 14 3 MD14 3 8 H FEB22 HCAN 16 4P 4P Message data 14 4 MD14 4 8 H FEB23 HCAN 16 4P 4P Message data 14 5 MD14 5 8 H FEB24 HCAN 16 4P 4P Message data 14 6 MD14 6...

Page 736: ...DR1_0 8 H FF20B SSU_0 16 3P 3P SS receive data register 2_0 SSRDR2_0 8 H FF20C SSU_0 16 3P 3P SS receive data register 3_0 SSRDR3_0 8 H FF20D SSU_0 16 3P 3P SS control register H_1 SSCRH_1 8 H FF210 S...

Page 737: ...16 3P 3P SS receive data register1_2 SSRDR1_2 8 H FF22B SSU_2 16 3P 3P SS receive data register2_2 SSRDR2_2 8 H FF22C SSU_2 16 3P 3P SS receive data register3_2 SSRDR3_2 8 H FF22D SSU_2 16 3P 3P Port...

Page 738: ...E TPU_6 16 2P 2P Timer control register_7 TCR_7 8 H FFB20 TPU_7 16 2P 2P Timer mode register_7 TMDR_7 8 H FFB21 TPU_7 16 2P 2P Timer I O control register_7 TIOR_7 8 H FFB22 TPU_7 16 2P 2P Timer interr...

Page 739: ...trol register_10 TCR_10 8 H FFB50 TPU_10 16 2P 2P Timer mode register_10 TMDR_10 8 H FFB51 TPU_10 16 2P 2P Timer I O control register_10 TIOR_10 8 H FFB52 TPU_10 16 2P 2P Timer interrupt enable regist...

Page 740: ...r control register P2ICR 8 H FFB91 I O port 8 2P 2P Port 3 input buffer control register P3ICR 8 H FFB92 I O port 8 2P 2P Port 4 input buffer control register P4ICR 8 H FFB93 I O port 8 2P 2P Port 5 i...

Page 741: ...JPCR 8 H FFBBA I O port 8 2P 2P Port K pull up MOS control register PKPCR 8 H FFBBB I O port 8 2P 2P Port 2 open drain control register P2ODR 8 H FFBBC I O port 8 2P 2P Port function control register...

Page 742: ...destination address register_2 DDAR_2 32 H FFC44 DMAC_2 16 2I 2I DMA offset register_2 DOFR_2 32 H FFC48 DMAC_2 16 2I 2I DMA transfer count register_2 DTCR_2 32 H FFC4C DMAC_2 16 2I 2I DMA block size...

Page 743: ...2I 3I Interrupt priority register F IPRF 16 H FFD4A INTC 16 2I 3I Interrupt priority register G IPRG 16 H FFD4C INTC 16 2I 3I Interrupt priority register I IPRI 16 H FFD50 INTC 16 2I 3I Interrupt prio...

Page 744: ...register_3 SSR_3 8 H FFE8C SCI_3 8 2P 2P Receive data register_3 RDR_3 8 H FFE8D SCI_3 8 2P 2P Smart card mode register_3 SCMR_3 8 H FFE8E SCI_3 8 2P 2P Serial mode register_4 SMR_4 8 H FFE90 SCI_4 8...

Page 745: ...r_5 TIOR_5 8 H FFEF2 TPU_5 2 16 2P 2P Timer interrupt enable register_5 TIER_5 8 H FFEF4 TPU_5 2 16 2P 2P Timer status register_5 TSR_5 8 H FFEF5 TPU_5 2 16 2P 2P Timer counter_5 TCNT_5 16 H FFEF6 TPU...

Page 746: ...H FFF7B PPG 2 8 2P 2P Next data register H NDRH 8 H FFF7C PPG 2 8 2P 2P Next data register L NDRL 8 H FFF7D PPG 2 8 2P 2P Next data register H NDRH 8 H FFF7E PPG 2 8 2P 2P Next data register L NDRL 8...

Page 747: ...16 H FFFCA TPU_0 2 16 2P 2P Timer general register C_0 TGRC_0 16 H FFFCC TPU_0 2 16 2P 2P Timer general register D_0 TGRD_0 16 H FFFCE TPU_0 2 16 2P 2P Timer control register_1 TCR_1 8 H FFFD0 TPU_1...

Page 748: ...egister H_3 TIORH_3 8 H FFFF2 TPU_3 2 16 2P 2P Timer I O control register L_3 TIORL_3 8 H FFFF3 TPU_3 2 16 2P 2P Timer interrupt enable register_3 TIER_3 8 H FFFF4 TPU_3 2 16 2P 2P Timer status regist...

Page 749: ...XPR2 TXPR1 TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8 TXCR TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8 TXACK TXACK7 TXACK6 TXACK5 TXACK4...

Page 750: ...DLC3 DLC2 DLC1 DLC0 MC0 2 MC0 3 MC0 4 MC0 5 ID 20 ID 19 ID 18 RTR IDE ID 17 ID 16 MC0 6 ID 28 ID 27 ID 26 ID 25 ID 24 ID 23 ID 22 ID 21 MC0 7 ID 7 ID 6 ID 5 ID 4 ID 3 ID 2 ID 1 ID 0 MC0 8 ID 15 ID 14...

Page 751: ...15 ID 14 ID 13 ID 12 ID 11 ID 10 ID 9 ID 8 MC4 1 DLC3 DLC2 DLC1 DLC0 MC4 2 MC4 3 MC4 4 MC4 5 ID 20 ID 19 ID 18 RTR IDE ID 17 ID 16 MC4 6 ID 28 ID 27 ID 26 ID 25 ID 24 ID 23 ID 22 ID 21 MC4 7 ID 7 ID...

Page 752: ...ID 17 ID 16 MC7 6 ID 28 ID 27 ID 26 ID 25 ID 24 ID 23 ID 22 ID 21 MC7 7 ID 7 ID 6 ID 5 ID 4 ID 3 ID 2 ID 1 ID 0 MC7 8 ID 15 ID 14 ID 13 ID 12 ID 11 ID 10 ID 9 ID 8 MC8 1 DLC3 DLC2 DLC1 DLC0 MC8 2 MC8...

Page 753: ...14 ID 13 ID 12 ID 11 ID 10 ID 9 ID 8 MC11 1 DLC3 DLC2 DLC1 DLC0 MC11 2 MC11 3 MC11 4 MC11 5 ID 20 ID 19 ID 18 RTR IDE ID 17 ID 16 MC11 6 ID 28 ID 27 ID 26 ID 25 ID 24 ID 23 ID 22 ID 21 MC11 7 ID 7 ID...

Page 754: ...10 ID 9 ID 8 MC14 1 DLC3 DLC2 DLC1 DLC0 MC14 2 MC14 3 MC14 4 MC14 5 ID 20 ID 19 ID 18 RTR IDE ID 17 ID 16 MC14 6 ID 28 ID 27 ID 26 ID 25 ID 24 ID 23 ID 22 ID 21 MC14 7 ID 7 ID 6 ID 5 ID 4 ID 3 ID 2 I...

Page 755: ...6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 Module MD1 1 HCAN MD1 2 MD1 3 MD1 4 MD1 5 MD1 6 MD1 7 MD1 8 MD2 1 MD2 2 MD2 3 MD2 4 MD2 5 MD2 6 MD2 7 MD2 8 MD...

Page 756: ...6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 Module MD4 5 HCAN MD4 6 MD4 7 MD4 8 MD5 1 MD5 2 MD5 3 MD5 4 MD5 5 MD5 6 MD5 7 MD5 8 MD6 1 MD6 2 MD6 3 MD6 4 MD...

Page 757: ...29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 Module MD8 1 HCAN MD8 2 MD8 3 MD8 4 MD8 5 MD8 6 MD8 7 MD8 8 MD9 1 MD9 2 MD9 3 MD9 4 MD9 5 MD9 6 MD9 7 MD9 8 MD10 1 M...

Page 758: ...5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 Module MD11 5 HCAN MD11 6 MD11 7 MD11 8 MD12 1 MD12 2 MD12 3 MD12 4 MD12 5 MD12 6 MD12 7 MD12 8 MD13 1 MD13 2 MD13 3 MD13 4...

Page 759: ...CSS1 CSS0 SSU_0 SSCRL_0 SSUMS SRES DATS1 DATS0 SSMR_0 MLS CPOS CPHS CKS2 CKS1 CKS0 SSER_0 TE RE TEIE TIE RIE CEIE SSSR_0 ORER TEND TDRE RDRF CE SSCR2_0 SDOS SSCKOS SCSOS TENDSTS SCSATS SSODTS SSTDR0_0...

Page 760: ..._1 SSRDR3_1 SSCRH_2 MSS BIDE SOL SOLP SCKS CSS1 CSS0 SSU_2 SSCRL_2 SSUMS SRES DATS1 DATS0 SSMR_2 MLS CPOS CPHS CKS2 CKS1 CKS0 SSER_2 TE RE TEIE TIE RIE CEIE SSSR_2 ORER TEND TDRE RDRF CE SSCR2_2 SDOS...

Page 761: ...ADST CH3 CH2 CH1 CH0 ADCR_1 TRGS1 TRGS0 SCANE SCANS CKS1 CKS0 TSTRB CST5 CST4 CST3 CST2 CST1 CST0 TPU TSYRB SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 TCR_6 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TP...

Page 762: ...TGIEA TSR_7 TCFD TCFU TCFV TGFB TGFA TCNT_7 TGRA_7 TGRB_7 TCR_8 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_8 TMDR_8 MD2 MD1 MD0 TIOR_8 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_8 TCIEU TCIEV TGI...

Page 763: ...CLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_10 TMDR_10 MD2 MD1 MD0 TIOR_10 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_10 TCIEU TCIEV TGIEB TGIEA TSR_10 TCFD TCFU TCFV TGFB TGFA TCNT_10 TGRA_10 TGRB...

Page 764: ...CR P61ICR P60ICR PAICR PA7ICR PA6ICR PA5ICR PA4ICR PA3ICR PA2ICR PA1ICR PDICR PD7ICR PD6ICR PD5ICR PD4ICR PD3ICR PD2ICR PD1ICR PD0ICR PORTH PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PORTJ PJ7 PJ6 PJ5 PJ4 PJ3 PJ...

Page 765: ...PFCRB ITS14 ITS13 ITS12 ITS11 ITS10 ITS9 ITS8 SSIER SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 INTC SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 DSAR_0 DMAC_0 DDAR_0 DOFR_0 DTCR_0 DBSR_0 BKSZH31 BKSZH30 BKSZH...

Page 766: ...SARA2 SARA1 SARA0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0 DSAR_1 DMAC_1 DDAR_1 DOFR_1 DTCR_1 DBSR_1 BKSZH31 BKSZH30 BKSZH29 BKSZH28 BKSZH27 BKSZH26 BKSZH25 BKSZH24 BKSZH23 BKSZH22 BKSZH21 BKSZH20 BKSZH19...

Page 767: ...SARA2 SARA1 SARA0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0 DSAR_2 DMAC_2 DDAR_2 DOFR_2 DTCR_2 DBSR_2 BKSZH31 BKSZH30 BKSZH29 BKSZH28 BKSZH27 BKSZH26 BKSZH25 BKSZH24 BKSZH23 BKSZH22 BKSZH21 BKSZH20 BKSZH19...

Page 768: ...SARA2 SARA1 SARA0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0 DSAR_3 DMAC_3 DDAR_3 DOFR_3 DTCR_3 DBSR_3 BKSZH31 BKSZH30 BKSZH29 BKSZH28 BKSZH27 BKSZH26 BKSZH25 BKSZH24 BKSZH23 BKSZH22 BKSZH21 BKSZH20 BKSZH19...

Page 769: ...IPRB IPRB14 IPRB13 IPRB12 IPRB10 IPRB9 IPRB8 IPRB6 IPRB5 IPRB4 IPRB2 IPRB1 IPRB0 IPRC IPRC14 IPRC13 IPRC12 IPRC10 IPRC9 IPRC8 INTC IPRC6 IPRC5 IPRC4 IPRC2 IPRC1 IPRC0 IPRD IPRD14 IPRD13 IPRD12 IPRD10...

Page 770: ...Q7SF IRQ6SR IRQ6SF IRQ5SR IRQ5SF IRQ4SR IRQ4SF IRQ3SR IRQ3SF IRQ2SR IRQ2SF IRQ1SR IRQ1SF IRQ0SR IRQ0SF BCR2 IBCCS PWDBE BSC RAMER RAMS RAM2 RAM1 RAM0 MDCR MDS3 MDS2 MDS1 MDS0 SYSTEM SYSCR MACS RAME FL...

Page 771: ...STOP BCP1 MP BCP0 CKS1 CKS0 SCI_4 BRR_4 SCR_4 1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDR_4 SSR_4 1 TDRE RDRF ORER FER ERS PER TEND MPB MPBT RDR_4 SCMR_4 SDIR SINV SMIF FCCS FLER SCO FLASH FPCS PPVS FECS...

Page 772: ...IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E ISR IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F PORT1 P17 P16 P15 P14 P13 P12 P11 P10 I O port PORT2 P23 P22 P21...

Page 773: ...DER10 NDER9 NDER8 NDERL NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 PODRH POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 PODRL POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 NDRH NDR15 NDR14 NDR13 NDR12 N...

Page 774: ...G1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_0 2 TMDR_0 BFB BFA MD2 MD1 MD0 TIORH_0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_0 TTGE TCIEV TGIED TGIEC TGIEB TGIEA...

Page 775: ...TGE TCIEU TCIEV TGIEB TGIEA TSR_2 TCFD TCFU TCFV TGFB TGFA TCNT_2 TGRA_2 TGRB_2 TCR_3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_3 2 TMDR_3 BFB BFA MD2 MD1 MD0 TIORH_3 IOB3 IOB2 IOB1 IOB0 IOA...

Page 776: ...TXACK Initialized Initialized Initialized Initialized ABACK Initialized Initialized Initialized Initialized RXPR Initialized Initialized Initialized Initialized RFPR Initialized Initialized Initializ...

Page 777: ...Sleep Module Stop All Module Clock Stop Software Standby Hardware Standby MC1 1 HCAN MC1 2 MC1 3 MC1 4 MC1 5 MC1 6 MC1 7 MC1 8 MC2 1 MC2 2 MC2 3 MC2 4 MC2 5 MC2 6 MC2 7 MC2 8 MC3 1 MC3 2 MC3 3 MC3 4...

Page 778: ...Sleep Module Stop All Module Clock Stop Software Standby Hardware Standby MC4 5 HCAN MC4 6 MC4 7 MC4 8 MC5 1 MC5 2 MC5 3 MC5 4 MC5 5 MC5 6 MC5 7 MC5 8 MC6 1 MC6 2 MC6 3 MC6 4 MC6 5 MC6 6 MC6 7 MC6 8...

Page 779: ...Module Stop All Module Clock Stop Software Standby Hardware Standby MC8 1 HCAN MC8 2 MC8 3 MC8 4 MC8 5 MC8 6 MC8 7 MC8 8 MC9 1 MC9 2 MC9 3 MC9 4 MC9 5 MC9 6 MC9 7 MC9 8 MC10 1 MC10 2 MC10 3 MC10 4 MC...

Page 780: ...Stop All Module Clock Stop Software Standby Hardware Standby MC11 5 HCAN MC11 6 MC11 7 MC11 8 MC12 1 MC12 2 MC12 3 MC12 4 MC12 5 MC12 6 MC12 7 MC12 8 MC13 1 MC13 2 MC13 3 MC13 4 MC13 5 MC13 6 MC13 7 M...

Page 781: ...ep Module Stop All Module Clock Stop Software Standby Hardware Standby MC15 1 HCAN MC15 2 MC15 3 MC15 4 MC15 5 MC15 6 MC15 7 MC15 8 MD0 1 MD0 2 MD0 3 MD0 4 MD0 5 MD0 6 MD0 7 MD0 8 MD1 1 MD1 2 MD1 3 MD...

Page 782: ...Sleep Module Stop All Module Clock Stop Software Standby Hardware Standby MD2 5 HCAN MD2 6 MD2 7 MD2 8 MD3 1 MD3 2 MD3 3 MD3 4 MD3 5 MD3 6 MD3 7 MD3 8 MD4 1 MD4 2 MD4 3 MD4 4 MD4 5 MD4 6 MD4 7 MD4 8...

Page 783: ...Sleep Module Stop All Module Clock Stop Software Standby Hardware Standby MD6 1 HCAN MD6 2 MD6 3 MD6 4 MD6 5 MD6 6 MD6 7 MD6 8 MD7 1 MD7 2 MD7 3 MD7 4 MD7 5 MD7 6 MD7 7 MD7 8 MD8 1 MD8 2 MD8 3 MD8 4...

Page 784: ...e Stop All Module Clock Stop Software Standby Hardware Standby MD9 5 HCAN MD9 6 MD9 7 MD9 8 MD10 1 MD10 2 MD10 3 MD10 4 MD10 5 MD10 6 MD10 7 MD10 8 MD11 1 MD11 2 MD11 3 MD11 4 MD11 5 MD11 6 MD11 7 MD1...

Page 785: ...e Clock Stop Software Standby Hardware Standby MD13 1 HCAN MD13 2 MD13 3 MD13 4 MD13 5 MD13 6 MD13 7 MD13 8 MD14 1 MD14 2 MD14 3 MD14 4 MD14 5 MD14 6 MD14 7 MD14 8 MD15 1 MD15 2 MD15 3 MD15 4 MD15 5 M...

Page 786: ...nitialized Initialized Initialized Initialized SSRDR2_0 Initialized Initialized Initialized Initialized SSRDR3_0 Initialized Initialized Initialized Initialized SSCRH_1 Initialized Initialized Initial...

Page 787: ...nitialized Initialized SSTDR1_2 Initialized Initialized Initialized Initialized SSTDR2_2 Initialized Initialized Initialized Initialized SSTDR3_2 Initialized Initialized Initialized Initialized SSRDR0...

Page 788: ..._6 Initialized TCNT_6 Initialized TGRA_6 Initialized TGRB_6 Initialized TGRC_6 Initialized TGRD_6 Initialized TCR_7 Initialized TPU_7 TMDR_7 Initialized TIOR_7 Initialized TIER_7 Initialized TSR_7 Ini...

Page 789: ...tialized TCNT_9 Initialized TGRA_9 Initialized TGRB_9 Initialized TGRC_9 Initialized TGRD_9 Initialized TCR_10 Initialized TPU_10 TMDR_10 Initialized TIOR_10 Initialized TIER_10 Initialized TSR_10 Ini...

Page 790: ...ized PDDDR Initialized P1ICR Initialized P2ICR Initialized P3ICR Initialized P4ICR Initialized P5ICR Initialized P6ICR Initialized PAICR Initialized PDICR Initialized PORTH PORTJ PORTK PHDR Initialize...

Page 791: ...TC DSAR_0 Initialized DMAC_0 DDAR_0 Initialized DOFR_0 Initialized DTCR_0 Initialized DBSR_0 Initialized DMDR_0 Initialized DACR_0 Initialized DSAR_1 Initialized DMAC_1 DDAR_1 Initialized DOFR_1 Initi...

Page 792: ...itialized DMRSR_0 Initialized DMAC_0 DMRSR_1 Initialized DMAC_1 DMRSR_2 Initialized DMAC_2 DMRSR_3 Initialized DMAC_3 IPRA Initialized INTC IPRB Initialized IPRC Initialized IPRD Initialized IPRE Init...

Page 793: ...Initialized Initialized Initialized Initialized SSR_3 Initialized Initialized Initialized Initialized RDR_3 Initialized Initialized Initialized Initialized SCMR_3 Initialized SMR_4 Initialized SCI_4 B...

Page 794: ...d TIER_4 Initialized TSR_4 Initialized TCNT_4 Initialized TGRA_4 Initialized TGRB_4 Initialized TCR_5 Initialized TPU_5 TMDR_5 Initialized TIOR_5 Initialized TIER_5 Initialized TSR_5 Initialized TCNT_...

Page 795: ...Initialized PPG PMR Initialized NDERH Initialized NDERL Initialized PODRH Initialized PODRL Initialized NDRH Initialized NDRL Initialized ADDRA_0 Initialized A D_0 ADDRB_0 Initialized ADDRC_0 Initiali...

Page 796: ...TSR_0 Initialized TCNT_0 Initialized TGRA_0 Initialized TGRB_0 Initialized TGRC_0 Initialized TGRD_0 Initialized TCR_1 Initialized TPU_1 TMDR_1 Initialized TIOR_1 Initialized TIER_1 Initialized TSR_1...

Page 797: ...Software Standby Hardware Standby TCR_3 Initialized TPU_3 TMDR_3 Initialized TIORH_3 Initialized TIORL_3 Initialized TIER_3 Initialized TSR_3 Initialized TCNT_3 Initialized TGRA_3 Initialized TGRB_3...

Page 798: ...Section 20 List of Registers Rev 3 00 Mar 14 2006 Page 760 of 804 REJ09B0104 0300 Downloaded from Elcodis com electronic components distributor...

Page 799: ...Vin 0 3 to AVCC0 0 3 V Analog power supply voltage AVCC0 0 3 to 7 0 V AVCC1 0 3 to 7 0 V Analog input voltage port 4 VAN 0 3 to AVCC1 0 3 V Analog input voltage port 5 VAN 0 3 to AVCC0 0 3 V Operating...

Page 800: ...0 3 V EXTAL VCC 0 7 VCC 0 3 Other input pins VCC 0 7 VCC 0 3 Port 4 AVCC1 0 7 AVCC1 0 3 Input high voltage except Schmitt trigger input pin Port 5 AVCC0 0 7 AVCC0 0 3 RES MD NMI VIL 0 3 VCC 0 1 V EXT...

Page 801: ...op mode 5 35 45 Analog power During A D conversion AICC0 3 5 5 AVCC0 5 0 V supply current Standby for A D conversion 10 100 A During A D conversion AICC1 3 5 5 mA AVCC1 5 0 V Standby for A D conversio...

Page 802: ...sible output high current per pin All output pins IOH 2 0 mA Permissible output high current total Total of all output pins IOH 30 mA Caution To protect the LSI s reliability do not exceed the output...

Page 803: ...ns Clock rising time tCr 5 ns Clock falling time tCf 5 ns Oscillation settling time after reset crystal tOSC1 20 ms Figure 21 4 Oscillation settling time after leaving software standby mode crystal t...

Page 804: ...2 I NMI NMI exception handling NMIEG 1 SSBY 1 NMI exception handling SLEEP instruction NMIEG SSBY Figure 21 3 Oscillation Settling Timing after Software Standby Mode EXTAL VCC RES I tDEXT tOSC1 Figure...

Page 805: ...cations Item Symbol Min Max Unit Test Conditions RES setup time tRESS 200 ns Figure 21 6 RES pulse width tRESW 20 tcyc NMI setup time tNMIS 150 ns Figure 21 7 NMI hold time tNMIH 10 ns NMI pulse width...

Page 806: ...5 V AVCC1 4 5 V to 5 5 V VSS AVSS 0 V P 8 to 35 MHz Ta 40 C to 85 C wide range specifications Item Symbol Min Max Unit Test Conditions I O ports Output data delay time tPWD 40 ns Figure 21 8 Input da...

Page 807: ...20 ns Measurement voltages VCC 0 3 V to VCC 0 7 V Asynchronous tScyc 30 tcyc Figure 21 13 Output clock cycle Clocked synchronous 4 Output clock pulse width tSCKW 0 4 0 6 tScyc Output clock rise time t...

Page 808: ...ycle time Master tSUcyc 4 256 tcyc Figure 21 17 Slave 4 256 Figure 21 18 Clock high pulse width Master tHI 80 ns Figure 21 19 Slave 80 Figure 21 20 Clock low pulse width Master tLO 80 ns Slave 80 Cloc...

Page 809: ...ceived as the signals in synchronization with every other rising edge of the P clock see figure 21 16 The HCAN output signals are also asynchronous signals however change their levels based on every o...

Page 810: ...CA11 TIOCB6 to TIOCB11 TIOCC6 TIOCC9 TIOCD6 and TIOCD9 2 Supported only by the H8SX 1527 Figure 21 10 TPU Input Output Timing P TCLKA to TCLKD TCLKE to TCLKH tTCKWL tTCKWH tTCKS tTCKS Note Supported o...

Page 811: ...smit data RxD3 RxD4 receive data Figure 21 14 SCI Input Output Timing Clocked Synchronous Mode P ADTRG0 ADTRG1 tTRGS Figure 21 15 A D Converter External Trigger Input Timing HTxD transmit data HRxD re...

Page 812: ...t SSI input tLEAD tSU tH tOD tFALL tRISE tSUcyc tLAG tOH tLO tHI tHI tLO tTD Figure 21 17 SSU Timing Master CPHS 1 tLEAD tSU tH tOD tFALL tRISE tSUcyc tLAG tOH tLO tHI tHI tLO tTD SSCK output CPOS 0 S...

Page 813: ...tHI tLO tH SSCK input CPOS 0 SCS input SSCK input CPOS 1 SSO input SSI output Figure 21 19 SSU Timing Slave CPHS 1 tLEAD tFALL tRISE tSUcyc tLAG tTD tREL tOH tOD tSU tSA tLO tHI tHI tLO tH SSCK input...

Page 814: ...AVCC1 4 5 V to 5 5 V VSS AVSS 0 V P 8 to 35 MHz Ta 40 C to 85 C wide range specifications Item Min Typ Max Unit Resolution 10 10 10 Bit Conversion time 7 4 200 s Analog input capacitance 20 pF Permiss...

Page 815: ...00 ms 64 kbyte block Programming time total 1 2 4 tP 5 15 s 256 kbytes Ta 25 C memory filled with 0 Erase time total 1 2 4 tE 5 15 s 256 kbytes Ta 25 C Programming erase time total 1 2 4 tPE 10 30 s 2...

Page 816: ...Section 21 Electrical Characteristics Rev 3 00 Mar 14 2006 Page 778 of 804 REJ09B0104 0300 Downloaded from Elcodis com electronic components distributor...

Page 817: ...t Name MCU Operating Mode Reset Software Standby Mode Port 1 All Hi Z Keep Port 2 All Hi Z Keep Port 3 All Hi Z Keep Port 4 All Hi Z Hi Z Port 5 All Hi Z Hi Z Port 6 All Hi Z Keep Port A All Hi Z Keep...

Page 818: ...804 REJ09B0104 0300 B Product Lineup Product Classification Product Model Marking Package Package Code H8SX 1527 R5F61527 R5F61527 PRQP0100KB A FP 100M H8SX 1525 R5F61525 R5F61525 Downloaded from Elco...

Page 819: ...ce Symbol Dimension in Millimeters Min Nom Max 1 0 14 1 0 0 10 0 8 0 5 0 12 0 17 0 22 0 17 0 22 0 27 0 00 0 12 0 25 3 05 15 8 16 0 16 2 2 70 14 0 20 0 15 0 4 0 5 0 6 0 08 16 2 16 0 15 8 1 0 1 2 3 p E...

Page 820: ...Appendix Rev 3 00 Mar 14 2006 Page 782 of 804 REJ09B0104 0300 Downloaded from Elcodis com electronic components distributor...

Page 821: ...14 to 0 5 6 5 DMAC Activation by Interrupt 1 Selection of Interrupt Sources 119 Added The selected activation source is input to the DMAC through the select circuit When transfer by an on chip module...

Page 822: ...MA Controller DMAC 7 2 6 DMA Mode Control Register DMDR Bit 5 149 Amended Data Transfer Acknowledge This bit is valid while the DMA transfer is performed by the on chip module interrupt This bit decid...

Page 823: ...Section 8 I O Ports 8 1 Register Descriptions Figure 8 1 Port Block Diagram 211 Amended Legend RDR DR read RPOR PORT read RICR ICR read RPCR PCR read RODR ODR read 8 1 5 Pull Up MOS Control Register P...

Page 824: ...ile the corresponding interrupt is enabled be sure to read the flag after writing 0 to it 12 4 2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 407 Amended M 0 5 L 0 5 F 1 F 10...

Page 825: ...ded 14 4 5 SSU Mode Figure 14 4 Example of Initial Settings in SSU Mode 530 Amended Start setting initial values 4 End Specify MLS CPOS CPHS CKS2 CKS1 and CKS0 bits in SSMR Specify SDOS SSCKOS SCSOS T...

Page 826: ...r TE and RE in SSER to 0 Error processing End transmission reception 14 4 7 Clock Synchronous Communication Mode Figure 14 12 Example of Initial Settings in Clock Synchronous Communication Mode 539 Am...

Page 827: ...eception 544 Amended Start Initial setting Transmission reception started TE 1 RE 1 1 2 Read TDRE in SSSR Yes No No Read TEND in SSSR TEND 1 Yes No Has the 1 bit transfer period elapsed Consecutive da...

Page 828: ...d channels until this bit is cleared to 0 by software or a reset Section 16 RAM 567 Amended Product Classification RAM Size RAM Addresses H8SX 1527 12 kbytes H FF9000 to H FFBFFF Flash memory version...

Page 829: ...alues for the erase block numbers range from 0 to 11 H 00000000 to H 0000000B A value of 0 corresponds to block EB0 and a value of 11 corresponds to block EB11 An error occurs when a value outside the...

Page 830: ...xecuted The initialization program is downloaded together with the programming program to the on chip RAM The entry point of the initialization program is at the address which is 32 bytes after DLTOP...

Page 831: ...dress which is 16 bytes after DLTOP start address of the download destination specified by FTDAR Call the subroutine to execute erasure by using the following steps The general registers other than ER...

Page 832: ...for Erasing User MAT in User Boot Mode 616 Amended Yes No Start erasing procedure program Set FKEY to H A5 Yes No Download error processing Set the FPEFEQ parameter End erasing procedure program FPFR...

Page 833: ...10 To program the flash memory the program data and program must be allocated to addresses which are higher than those of the external interrupt vector table and H FF must be written to all the system...

Page 834: ...12 STS4 0 R W 11 STS3 1 R W 10 STS2 1 R W 9 STS1 1 R W 8 STS0 1 R W Bit Bit Name Initial Value R W 7 0 R W 6 0 R W 5 0 R W 4 0 R W 3 0 R W 2 0 R W 1 0 R W 0 0 R W Bit Bit Name Initial Value R W 15 SS...

Page 835: ...ICK1 ICK0 PCK2 PCK1 PCK0 BCK2 BCK1 BCK0 SBYCR SSBY STS4 STS3 STS2 STS1 STS0 Section 21 Electrical Characteristics 761 Amended Item Symbol Value Unit Regular specifications 20 to 75 Operating temperat...

Page 836: ...racteristics Table 21 8 Flash Memory Characteristics 762 to 777 Conditions VCC 4 5 V to 5 5 V AVCC0 4 5 V to 5 5 V AVCC1 4 5 V to 5 5 V VSS AVSS 0 V 1 Ta 20 C to 75 C regular specifications Ta 40 C to...

Page 837: ...fer segment 487 Bus access modes 168 Bus arbitration 131 Bus configuration 127 Bus controller BSC 125 Bus released state 64 C CAN bus interface 503 Clock 408 Clock pulse generator 661 Clock synchronou...

Page 838: ...AN sleep mode 498 HCAN transmission setting 507 I I O ports 205 ID code 416 Illegal instruction 83 Input buffer control register 213 Input capture function 303 Internal bus 129 Internal interrupts 104...

Page 839: ...ster 215 Port register 213 Port states in each pin state 779 Power down modes 671 Processing states 64 Product lineup 780 Program execution state 64 Program stop state 64 Programmable pulse generator...

Page 840: ...68 705 732 755 MSTPCRA 675 706 732 755 MSTPCRB 675 706 732 755 MSTPCRC 678 706 732 755 NDERH 347 708 735 757 NDERL 347 708 735 757 NDRH 350 708 735 757 NDRL 350 708 735 757 ODR 215 703 727 753 PC 30 P...

Page 841: ...p mode 671 672 680 Slot illegal instruction 84 Smart card interface 429 Software protection 624 Software standby mode 671 672 681 SSU mode 530 Stack status after exception handling 85 Standard serial...

Page 842: ...Rev 3 00 Mar 14 2006 Page 804 of 804 REJ09B0104 0300 Write data buffer function for peripheral module 130 Downloaded from Elcodis com electronic components distributor...

Page 843: ...3 00 Mar 14 2006 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions Corp 2006 Renesas Technol...

Page 844: ...td 7th Floor North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2730 6071 Renesas Technology Taiwan Co Ltd 10th Floor No 99 Fushing Nor...

Page 845: ...Downloaded from Elcodis com electronic components distributor...

Page 846: ...H8SX 1520 Group Hardware Manual Downloaded from Elcodis com electronic components distributor...

Reviews:

No comments

Related manuals for H8SX series

Brand: SAF Pages: 30

Brand: T&D Pages: 122

Brand: STONEFLY Pages: 48

Brand: Industrex Pages: 51

Brand: FOR-A Pages: 39

Brand: Baicells Pages: 10

Brand: ZALMAN Pages: 7

Brand: Uniden Pages: 5

Brand: ICOP Technology Pages: 34

Brand: Xtreme Pages: 83

Brand: Vacron Pages: 16

Brand: Meinberg Pages: 14

Brand: EZCast Pro Pages: 4

Brand: ekwb Pages: 2

Brand: Magewell Pages: 10

Brand: Z3 Technology Pages: 18

Brand: Keithley Pages: 108

Brand: Microcomputer Systems Pages: 21

Brands by name

0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Popular brands

Load more brands