Renesas H8SX series, Hardware Manual

Page: 248 / 846

Section 8 I/O Ports
Rev. 3.00 Mar. 14, 2006 Page 210 of 804
REJ09B0104-0300
8.1 Register Descriptions
Table 8.2 lists each port registers.
Table 8.2 Register Configuration in Each Port
Registers
Port
Number of
Pins
DDR DR PORT ICR PCR ODR PHRTIDR
Port 1 8 O O O O
  
Port 2 *
1
4 O O O O

O

Port 3 8 O O O O
  
Port 4 8
 
O O
  
Port 5 8
 
O O
  
Port 6
*
2
7 O O O O
  
Port A
*
3
7 O O O O
  
Port D 8 O O O O O
 
Port H 8 O O O O O

O
Port J 8 O O O O O
 
Port K 8 O O O O O
 
[Legend]
O: Register exists

: No register exists
Notes: 1. The lower four bits are valid and the upper four bits are reserved. The write value
should always be the initial value.
2. The lower seven bits are valid and the upper one bit is reserved. The write value should
always be the initial value.
3. The upper seven bits are valid and the lower one bit is reserved. The write value should
always be the initial value.
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