Section 4 Exception Handling
Rev. 3.00 Mar. 14, 2006 Page 76 of 804
REJ09B0104-0300
Table 4.3
Calculation Method of Exception Handling Vector Table Address
Exception Source
Calculation Method of Vector Table Address
Reset, CPU address error Vector table address = (vector table address offset)
Other than above
Vector table address = VBR
+
(vector table address offset)
[Legend]
VBR: Vector base register
Vector table address offset: See table 4.2.
4.3 Reset
A reset has priority over any other exception. When the
RES
pin goes low, all processing halts and
this LSI enters the reset state. To ensure that this LSI is reset, hold the
RES
pin low for at least 20
ms when the power is turned on. When operation is in progress, hold the
RES
pin low for at least
20 cycles.
The chip can also be reset by overflow of the watchdog timer. For details, see section 11,
Watchdog Timer (WDT).
A reset initializes the internal state of the CPU and the registers of the on-chip peripheral modules.
The interrupt control mode is 0 immediately after a reset.
4.3.1 Reset
Exception
Handling
When the
RES
pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, VBR is cleared to H'00000000, the T bit is cleared to 0 in EXR, and the I bits are
set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figure 4.1 shows an example of the reset sequence.
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