Renesas H8SX series, Hardware Manual, Page: 742 / 846

Section 20 List of Registers
Rev. 3.00 Mar. 14, 2006 Page 704 of 804
REJ09B0104-0300
Register Name Abbr.
Number
of Bits
Address Module
Data
Width
Access
Cycles
(Read/Write)
DMA source address
register_1 DSAR_1 32 H'FFC20 DMAC_1 16 2I
φ
/2I
φ
DMA destination address
register_1 DDAR_1 32 H'FFC24 DMAC_1 16 2I
φ
/2I
φ
DMA offset register_1 DOFR_1 32 H'FFC28 DMAC_1 16 2I
φ
/2I
φ
DMA transfer count register_1 DTCR_1 32 H'FFC2C DMAC_1 16 2I
φ
/2I
φ
DMA block size register_1 DBSR_1 32 H'FFC30 DMAC_1 16 2I
φ
/2I
φ
DMA mode control register_1 DMDR_1 32 H'FFC34 DMAC_1 16 2I
φ
/2I
φ
DMA address control
register_1 DACR_1 32 H'FFC38 DMAC_1 16 2I
φ
/2I
φ
DMA source address
register_2 DSAR_2 32 H'FFC40 DMAC_2 16 2I
φ
/2I
φ
DMA destination address
register_2 DDAR_2 32 H'FFC44 DMAC_2 16 2I
φ
/2I
φ
DMA offset register_2 DOFR_2 32 H'FFC48 DMAC_2 16 2I
φ
/2I
φ
DMA transfer count register_2 DTCR_2 32 H'FFC4C DMAC_2 16 2I
φ
/2I
φ
DMA block size register_2 DBSR_2 32 H'FFC50 DMAC_2 16 2I
φ
/2I
φ
DMA mode control register_2 DMDR_2 32 H'FFC54 DMAC_2 16 2I
φ
/2I
φ
DMA address control
register_2 DACR_2 32 H'FFC58 DMAC_2 16 2I
φ
/2I
φ
DMA source address
register_3 DSAR_3 32 H'FFC60 DMAC_3 16 2I
φ
/2I
φ
DMA destination address
register_3 DDAR_3 32 H'FFC64 DMAC_3 16 2I
φ
/2I
φ
DMA offset register_3 DOFR_3 32 H'FFC68 DMAC_3 16 2I
φ
/2I
φ
DMA transfer count register_3 DTCR_3 32 H'FFC6C DMAC_3 16 2I
φ
/2I
φ
DMA block size register_3 DBSR_3 32 H'FFC70 DMAC_3 16 2I
φ
/2I
φ
DMA mode control register_3 DMDR_3 32 H'FFC74 DMAC_3 16 2I
φ
/2I
φ
DMA address control
register_3 DACR_3 32 H'FFC78 DMAC_3 16 2I
φ
/2I
φ
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