Renesas H8SX series, Hardware Manual, Page: 154 / 846

Section 5 Interrupt Controller
Rev. 3.00 Mar. 14, 2006 Page 116 of 804
REJ09B0104-0300
5.6.3 Interrupt Exception Handling Sequence
Figure 5.5 shows the interrupt exception handling sequence. The example is for the case where
interrupt control mode 0 is set in maximum mode, and the program area and stack area are in on-
chip memory.
(12)
(10)
(6)
(4)
(2)
(1)
(5)
(7)
(9)
(11)
Instruction prefetch
Interrupt
acceptance
Interrupt level determination Wait for end of instruction
(3)
(8)
Instruction prefetch in interrupt handling routine
Internal
operation
Vector fetch
Stack
Internal
operation
Interrupt request signal Internal address bus Internal read signal Internal write signal Internal data bus I
φ
(1) (2) (4) (3) (5) (7)
Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) Instruction code (Not executed.) Instruction prefetch address (Not executed.) SP
−
2
SP
−
4
Saved PC and saved CCR Vector address Start address of interrupt handling routine (vector address contents) Start address of Interrupt handling routine ((11) = (10)) First instruction of interrupt handling routine
(6) (8) (9) (10) (11) (12)
Figure 5.5 Interrupt Exception Handling
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