Section 14 Synchronous Serial Communication Unit (SSU)
Rev. 3.00 Mar. 14, 2006 Page 525 of 804
REJ09B0104-0300
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Bit
Bit Name
Initial Value
R/W
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Bit
Bit Name
Initial Value
R/W
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Bit
Bit Name
Initial Value
R/W
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Bit
Bit Name
Initial Value
R/W
Table 14.3 Correspondence Between DATS Bit Setting and SSRDR
DATS[1:0]
(SSCRL[1:0])
SSRDR
00 01 10 11
(Setting
Invalid)
0
Valid Valid Valid Invalid
1 Invalid Valid Valid Invalid
2 Invalid Invalid Valid Invalid
3 Invalid Invalid Valid Invalid
14.3.9
SS Shift Register (SSTRSR)
SSTRSR is a shift register that transmits and receives serial data.
When data is transferred from SSTDR to SSTRSR, bit 0 of transmit data is bit 0 in the SSTDR
contents (MLS = 0: LSB first communication) and is bit 7 in the SSTDR contents (MLS = 1: MSB
first communication). The SSU transfers data from the LSB (bit 0) in SSTRSR to the SSO pin to
perform serial data transmission.
In reception, the SSU sets serial data that has been input via the SSI pin in SSTRSR from the LSB
(bit 0). When 1-byte data has been received, the SSTRSR contents are automatically transferred to
SSRDR. SSTRSR cannot be directly accessed by the CPU.
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