Section 9 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Mar. 14, 2006 Page 292 of 804
REJ09B0104-0300
9.3.5
Timer Status Register (TSR)
TSR indicates the status of each channel. The TPU has six TSR registers, one for each channel.
Bit
Bit Name
Initial Value
R/W
7
TCFD
1
R
6
—
1
R
5
TCFU
0
R/(W)
*
4
TCFV
0
R/(W)
*
3
TGFD
0
R/(W)
*
2
TGFC
0
R/(W)
*
1
TGFB
0
R/(W)
*
0
TGFA
0
R/(W)
*
Note:
*
Only 0 can be written to bits 5 to 0, to clear flags.
Bit Bit
Name
Initial
value R/W Description
7
TCFD
1
R
Count Direction Flag
Status flag that shows the direction in which TCNT counts
in channels 1, 2, 4, and 5.
In channels 0 and 3, bit 7 is reserved. It is a read-only bit
and cannot be modified.
0: TCNT counts down
1: TCNT counts up
6
1 R
Reserved
This is a read-only bit and cannot be modified.
5 TCFU
0 R/(W)
*
Underflow
Flag
Status flag that indicates that a TCNT underflow has
occurred when channels 1, 2, 4, and 5 are set to phase
counting mode.
In channels 0 and 3, bit 5 is reserved. It is a read-only bit
and cannot be modified.
[Setting condition]
•
When the TCNT value underflows (changes from
H'0000 to H'FFFF)
[Clearing condition]
•
When a 0 is written to TCFU after reading TCFU = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
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