Renesas H8SX series, Hardware Manual, Page: 379 / 846

Section 9 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Mar. 14, 2006 Page 341 of 804
REJ09B0104-0300
9.9.9 Conflict between TGR Write and Input Capture
If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 9.52 shows the timing in this case.
TCNT
P
φ
Input capture
signal
Address TGR address
Write
T1 T2
TGR write cycle
M
M TGR
Figure 9.52 Conflict between TGR Write and Input Capture
9.9.10 Conflict between Buffer Register Write and Input Capture
If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 9.53 shows the timing in this case.
TCNT
P
φ
Input capture
signal
Address
Buffer register
address
Write
T1 T2
Buffer register write cycle
N
N
TGR
Buffer register
M
M
Figure 9.53 Conflict between Buffer Register Write and Input Capture
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