Section 9 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Mar. 14, 2006 Page 270 of 804
REJ09B0104-0300
9.3.2
Timer Mode Register (TMDR)
TMDR sets the operating mode for each channel. The TPU has six TMDR registers, one for each
channel. TMDR register settings should be made only while TCNT operation is stopped.
7
-
1
R
6
-
1
R
5
BFB
0
R/W
4
BFA
0
R/W
3
MD3
0
R/W
2
MD2
0
R/W
1
MD1
0
R/W
0
MD0
0
R/W
Bit
Bit Name
Initial Value
R/W
Bit Bit
Name
Initial
Value R/W Description
7, 6
All
1
R
Reserved
These are read-only bits and cannot be modified.
5
BFB
0
R/W
Buffer Operation B
Specifies whether TGRB is to normally operate, or TGRB
and TGRD are to be used together for buffer operation.
When TGRD is used as a buffer register, TGRD input
capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is
reserved. It is a read-only bit and cannot be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation
4
BFA
0
R/W
Buffer Operation A
Specifies whether TGRA is to normally operate, or TGRA
and TGRC are to be used together for buffer operation.
When TGRC is used as a buffer register, TGRC input
capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is
reserved. It is a read-only bit and cannot be modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
3
2
1
0
MD3
MD2
MD1
MD0
0
0
0
0
R/W
R/W
R/W
R/W
Modes 3 to 0
Set the timer operating mode.
MD3 is a reserved bit. The write value should always
be 0. See table 9.14 for details.
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