Section 2 CPU
Rev. 3.00 Mar. 14, 2006 Page 65 of 804
REJ09B0104-0300
A transition to the reset state occurs whenever the
RES
signal goes low.
A transition can also be made to the reset state when the watchdog timer
overflows.
Note:
*
Reset state
*
Exception-handling
state
Request for exception
handling
End of exception
handling
Program execution
state
Bus-released state
Bus
request
End of bus request
Program stop state
SLEEP instruction
Interrupt
request
Bus request
End of
bus request
RES
= high
RES
= low
Figure 2.16 State Transitions
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