Section 4 Exception Handling
Rev. 3.00 Mar. 14, 2006 Page 80 of 804
REJ09B0104-0300
Bus Cycle
Type
Bus Master
Description
Address Error
Single address
transfer
DMAC
In single address transfer, the device to be
accessed with an address is in the external
memory space
No (normal)
In single address transfer, the device to be
accessed with an address is not in the
external memory space
Occurs
Notes: 1. For on-chip peripheral module space, see section 6, Bus Controller (BSC).
2. For the access reserved area, refer to figure 3.1 in section 3.4, Address Map. An
address error will not occur when the reserved area from H'FF8000 to H'FF8FFF is
accessed.
4.5.2
Address Error Exception Handling
When an address error occurs, address error exception handling starts after the bus cycle causing
the address error ends and current instruction execution completes. The address error exception
handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the address error is generated, the
start address of the exception service routine is loaded from the vector table to PC, and
program execution starts from that address.
Even though an address error occurs during a transition to an address error exception handling, the
address error is not accepted. This prevents an address error from occurring due to stacking for
exception handling, thereby preventing infinitive stacking.
If the SP contents are not a multiple of 2 when an address error exception handling occurs, the
stacked values (PC, CCR, and EXR) are undefined.
When an address error occurs, the following is performed to halt the DMAC.
•
ERRF bit in DMDR_0 of the DMAC is set to 1
•
DTE bits for all the channels of the DMAC are cleared to 0 and the DMAC is forced to halt
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