Section 12 Serial Communication Interface (SCI)
Rev. 3.00 Mar. 14, 2006 Page 392 of 804
REJ09B0104-0300
Bit Bit
Name
Initial
Value R/W Description
3 PER 0 R/(W)
*
Parity
Error
Indicates that a parity error has occurred during reception
in asynchronous mode and the reception ends
abnormally.
[Setting condition]
•
When a parity error is detected during reception
Receive data when the parity error occurs is
transferred to RDR, however, the RDRF flag is not
set. Note that when the PER flag is being set to 1, the
subsequent serial reception cannot be performed. In
clocked synchronous mode, serial transmission also
cannot continue.
[Clearing condition]
•
When 0 is written to PER after reading PER = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
Even when the RE bit in SCR is cleared, the PER bit
is not affected and retains its previous value.
2 TEND
1 R Transmit
End
[Setting conditions]
•
When the TE bit in SCR is 0
•
When TDRE = 1 at transmission of the last bit of a
transmit character
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE = 1
•
When a TXI interrupt request is issued allowing
DMAC to write data to TDR
1 MPB 0 R Multiprocessor
Bit
Stores the multiprocessor bit value in the receive frame.
When the RE bit in SCR is cleared to 0 its previous state
is retained.
0 MPBT
0 R/W
Multiprocessor
Bit
Transfer
Sets the multiprocessor bit value to be added to the
transmit frame.
Note:
*
Only 0 can be written, to clear the flag.
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