Section 15 A/D Converter
Rev. 3.00 Mar. 14, 2006 Page 559 of 804
REJ09B0104-0300
15.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
D
) passes after the ADST bit in ADCSR is set
to 1, then starts A/D conversion. Figure 15.5 shows the A/D conversion timing. Table 15.3
indicates the A/D conversion time.
As indicated in figure 15.5, the A/D conversion time (t
CONV
) includes t
D
and the input sampling time
(t
SPL
). The length of t
D
varies depending on the timing of the write access to ADCSR. The total
conversion time therefore varies within the ranges indicated in table 15.3.
In scan mode, the values given in table 15.3 apply to the first conversion time. The values given in
table 15.4 apply to the second and subsequent conversions. In either case, bits CKS1 and CKS0 in
ADCR should be set so that the conversion time is within the ranges indicated by the A/D
conversion characteristics.
(1)
(2)
t
D
t
SPL
t
CONV
P
φ
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1):
ADCSR write cycle
(2):
ADCSR address
t
D
:
A/D conversion start delay time
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
Figure 15.5 A/D Conversion Timing
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