Renesas H8SX series, Hardware Manual

Page: 134 / 846

Section 5 Interrupt Controller
Rev. 3.00 Mar. 14, 2006 Page 96 of 804
REJ09B0104-0300
5.3.5 IRQ Sense Control Registers H and L (ISCRH and ISCRL)
ISCRH and ISCRL select the source that generates an interrupt request on pins
IRQ14
to
IRQ0
.
Upon changing the setting of ISCR, IRQnF (n = 14 to 0) in ISR is often set to 1 accidentally
through an internal operation. In this case, an interrupt exception handling is executed if an IRQn
interrupt request is enabled. In order to prevent such an accidental interrupt from occurring, the
setting of ISCR should be changed while the IRQn interrupt is disabled, and then the IRQnF in
ISR should be cleared to 0.
•
ISCRH
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
15
—
0
R/W
14
—
0
R/W
13
IRQ14SR
0
R/W
12
IRQ14SF
0
R/W
11
IRQ13SR
0
R/W
10
IRQ13SF
0
R/W
9
IRQ12SR
0
R/W
8
IRQ12SF
0
R/W
7
IRQ11SR
0
R/W
6
IRQ11SF
0
R/W
5
IRQ10SR
0
R/W
4
IRQ10SF
0
R/W
3
IRQ9SR
0
R/W
2
IRQ9SF
0
R/W
1
IRQ8SR
0
R/W
0
IRQ8SF
0
R/W
•
ISCRL
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
15
IRQ7SR
0
R/W
14
IRQ7SF
0
R/W
13
IRQ6SR
0
R/W
12
IRQ6SF
0
R/W
11
IRQ5SR
0
R/W
10
IRQ5SF
0
R/W
9
IRQ4SR
0
R/W
8
IRQ4SF
0
R/W
7
IRQ3SR
0
R/W
6
IRQ3SF
0
R/W
5
IRQ2SR
0
R/W
4
IRQ2SF
0
R/W
3
IRQ1SR
0
R/W
2
IRQ1SF
0
R/W
1
IRQ0SR
0
R/W
0
IRQ0SF
0
R/W
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