Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar. 14, 2006 Page 150 of 804
REJ09B0104-0300
Bit Bit
Name
Initial
Value R/W Description
2
1
0
DMAP2
DMAP1
DMAP0
0
0
0
R/W
R/W
R/W
DMA Priority Level 2 to 0
Select the priority level of the DMAC. When the CPU
has priority over the DMAC, the DMAC masks a transfer
request and waits for the timing when the CPU priority
becomes lower than the DMAC priority. The priority
levels can be set to the individual channels. This bit is
valid when the CPUPCE bit in CPUPCR is set to 1.
000: Priority level 0 (low)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (high)
Note:
*
Only 0 can be written to, to clear the flag.
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