Section 9 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Mar. 14, 2006 Page 315 of 804
REJ09B0104-0300
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Example of PWM Mode Setting Procedure
Figure 9.21 shows an example of the PWM mode setting procedure.
Select counter clock
PWM mode
Select counter clearing source
Select waveform output level
<PWM mode>
[1]
[2]
[3]
Set TGR
[4]
Set PWM mode
[5]
Start count
[6]
[1] Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0 in
TCR.
[2] Use bits CCLR2 to CCLR0 in TCR to select the
TGR to be used as the TCNT clearing source.
[3] Use TIOR to designate TGR as an output
compare register, and select the initial value and
output
value.
[4] Set the cycle in TGR selected in [2], and set the
duty in the other TGRs.
[5] Select the PWM mode with bits MD3 to MD0 in
TMDR.
[6] Set the CST bit in TSTR to 1 to start the count
operation.
Figure 9.21 Example of PWM Mode Setting Procedure
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Examples of PWM Mode Operation
Figure 9.22 shows an example of PWM mode 1 operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the cycle, and the value set in TGRB register as the
duty cycle.
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