Renesas H8SX series, Hardware Manual

Page: 498 / 846

Section 13 Controller Area Network (HCAN)
Rev. 3.00 Mar. 14, 2006 Page 460 of 804
REJ09B0104-0300
13.3.6 Transmit Wait Cancel Register (TXCR)
TXCR cancels transmit wait messages in mailboxes.
15
TXCR7
0
R/W
14
TXCR6
0
R/W
13
TXCR5
0
R/W
12
TXCR4
0
R/W
11
TXCR3
0
R/W
8
—
0
R
10
TXCR2
0
R/W
9
TXCR1
0
R/W
Bit
Bit Name
Initial Value
R/W
7
TXCR15
0
R/W
6
TXCR14
0
R/W
5
TXCR13
0
R/W
4
TXCR12
0
R/W
3
TXCR11
0
R/W
0
TXCR8
0
R/W
2
TXCR10
0
R/W
1
TXCR9
0
R/W
Bit
Bit Name
Initial Value
R/W
Bit Bit Name
Initial
Value R/W
Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXCR7
TXCR6
TXCR5
TXCR4
TXCR3
TXCR2
TXCR1

TXCR15
TXCR14
TXCR13
TXCR12
TXCR11
TXCR10
TXCR9
TXCR8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
These bits cancel the transmit wait message in the
corresponding mailboxes 1 to 15. When TXCRn (n
= 1 to 15) is set to 1, the transmit wait message in
mailbox n is canceled.
[Clearing condition]
•
Completion of TXPR clearing when transmit
message is canceled normally
Bit 8 is reserved. This is a read-only bit and cannot
be modified.
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