Renesas 89HPES24T3G2ZBAL, User Manual

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IDT Configuration Registers
PES24T3G2 User Manual 8 - 13 February 22, 2012
Notes
CLS - Cache Line Size Register (0x00C)
PLTIMER - Primary Latency Timer (0x00D)
HDR - Header Type Register (0x00E)
BIST - Built-in Self Test Register (0x00F)
BAR0 - Base Address Register 0 (0x010)
15:8 SUB RO 0x04 Sub Class Code. This value indicates that the device is a PCI-
PCI bridge.
23:16 BASE RO 0x06 Base Class Code. This value indicates that the device is a
bridge.
Bit
Field
Field
Name
Type
Default
Value
Description
7:0 CLS RW 0x00 Cache Line Size. This field has no effect on the bridge’s func-
tionality but may be read and written by software.
This field is implemented for compatibility with legacy software.
Bit
Field
Field
Name
Type
Default
Value
Description
7:0 PLTIMER RO 0x00 Primary Latency Timer. Not applicable.
Bit
Field
Field
Name
Type
Default
Value
Description
7:0 HDR RO 0x01 Header Type. This value indicates a type 1 header with a single
function bridge layout.
Bit
Field
Field
Name
Type
Default
Value
Description
7:0 BIST RO 0x0 BIST. This value indicates that the bridge does not implement
BIST.
Bit
Field
Field
Name
Type
Default
Value
Description
31:0 BAR RO 0x0 Base Address Register. Not applicable.
Bit
Field
Field
Name
Type
Default
Value
Description